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  • MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
  • Memory
    - 64-Bit DDR4, 8 GByte maximum
    - Dual SPI boot Flash in parallel, 512 MByte maximum
  • User I/O
    - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
    - Serial transceiver: 4 x GTR + 16 x GTH
    - Transceiver clocks inputs and outputs
    - PLL clock generator inputs and outputs
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin
  • Si5345 - 10 output PLL
  • All power supplies on board, single 3.3V power source required
    - 14 on-board DCDC regulators and 13 LDOs
    - LP, FP, PL separately controlled power domains
  • Support for all boot modes (except NAND) and scenarios
  • Support for any combination of PS connected peripherals

Block Diagram

Image Modified

Figure 1: TE0808-04 Block Diagram

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Table 7: MIO-pin assignment of the Quad SPI Flash memory ICs

Boot Process

The boot source of the Zynq Ultrascale MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:

Boot Mode PinB2B Pin
PS_MODE0J2-109
PS_MODE1J2-107
PS_MODE2J2-105
PS_MODE3J2-103

Table 8: Boot mode pins on B2B connector J2


Following boot modes are possible on the TE0808 Ultrascale module by generating the corresponding 4-bit code by the pins 'PS_MODE0' ... 'PS_MODE3' (little endian alignment):

Boot ModeMode Pins [3:0]MIO LocationDescription
JTAG0x0JTAGDedicated PS interface.
QSPI320x2MIO[12:0]

Configured on module with dual QSPI Flash Memory.

32-bit addressing.
Supports single and dual parallel
configurations.
Stack and dual stack is not
supported.

SD00x3MIO[25:13]Supports SD 2.0.
SD10x5MIO[51:38]Supports SD 2.0.
eMMC_180x6MIO[22:13]Supports eMMC 4.5 at 1.8V.
USB 00111bMIO[52:63]Supports USB 2.0 and USB 3.0.
PJTAG_00x8MIO[29:26]PS JTAG connection 0 option.
SD1-LS0xEMIO[51:39]

Supports SD 3.0 with a required
SD 3.0 compliant level shifter.

Table 9: Selectable boot modes by dedicated boot mode pins

Full access to B2B connector. For Functional details see  ug1085 - Zynq ultrascale TRM (Boot Modes Section).

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On-board Peripherals

Flash

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 NameICDesignatorPS7MIONotes
SPI FlashN25Q256A11E1240EU7QSPI0MIO0 ... MIO5dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration
SPI FlashN25Q256A11E1240EU17QSPI0MIO7 ... MIO12as above

Table 810: Peripherals connected to the PS MIO-pins

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InputConnected toFrequencyNotes
IN0On-board Oscillator (U25)25.000000 MHz-
IN1B2B Connector pins J2-3, J2-1 (differential pair)UserAC decoupling required on base
IN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
OutputConnected toFrequencyNotes
OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault off
OUT1B230 CLK0UserDefault off
OUT2B229 CLK1UserDefault off
OUT3B228 CLK1UserDefault off
OUT4B505 CLK2UserDefault off
OUT5B505 CLK3UserDefault off
OUT6B128 CLK0UserDefault off
OUT7B2B Connector pins J2-7, J2-9 (differential pair)UserDefault off
OUT8B2B Connector pins J2-13, J2-15 (differential pair)UserDefault off
OUT9IN3 (Loop-back)UserDefault off
XA/XBQuartz (Y1)50.000 MHz-

Table 911: Programmable PLL clock generator input/output

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SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency Increment
PLL_LOLNJ2-85Loss Of Lock (low-active)
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual Input Switching
PLL_FDECJ2-94Frequency Decrement
PLL_RSTJ2-59
Device Reset (low-active)
PLL_SCL / PLL_SDAJ2-90 / J2-92

I²C interface, extern pull-ups needed for SCL- / SDA-line.

I²C address in current configuration: 1101000b

Table 1012: B2B connector pin-out of Si5345A programmable clock generator

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ClockFrequencyBank 503 PinConnected to
PS_CLK33.333333 MHzP20MEMS Oscillator, U32
PS_PAD (RTC)32.768 kHzR22/R23Quartz crystal, Y2

Table 1113: Reference clock-signals to PS configuration bank 503

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LED

ColorConnected toDescription and Notes
D1redDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

Table 1214: LED's description

Power and Power-On Sequence

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Power Input PinTypical Current
DCDCINTBD*
LP_DCDCTBD*
PL_DCINTBD*
PS_BATTTBD*

Table 1315: Maximum current of power supplies. *to be determined soon with reference design setup.

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Enable-SignalB2B Connector PinMax. VoltageNote Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)		 PG_PLJ2-104extern pull-up needed (max. voltage 'GT_DCDC'),
max. sink current 1 mA

TPS82085SIL /
NC7S08P5X data sheet

EN_DDRJ2-112DCDCINNC7S08P5X data sheet PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet PG_PSGTJ2-82extern pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet PG_GT_RJ2-91extern pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74401 data sheet
EN_GT_LJ2-79GT_DCDCNC7S08P5X data sheet PG_GT_LJ2-97extern pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_PLL_PWRJ2-776VTPS82085SIL data sheet PG_PLL_1V8J2-80extern pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS82085SIL data sheet

Table 1416: Recommended operation conditions of DCDC converter control signals

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Voltages on B2B
Connectors

B2B J1 PinB2B J2 PinB2B J3 PinB2B J4 Pin

Input/
Output

Note
PL_DCINJ1-151, J1-153, J1-157, J1-159---Input-
DCDCIN

-

J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159

--Input-
LP_DCDC-J2-138, J2-140, J2-142, J2-144--Input-
PS_BATT-J2-125--Input-
GT_DCDC--J3-157, J3-158, J3-159, J3-160-Input-
PLL_3V3--J3-152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--J3-151-OutputInternal voltage level
1.8V nominal output
PS_1V8-J2-99J3-148-Output

Internal voltage level
1.8V nominal output

PL_1V8J1-91, J1-121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-J2-135--Output

Internal voltage level
1.2V nominal output

Table 1517: Power rails of the MPSoC module on accessible connectors

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BankTypeSchematic Name / B2B connector PinsVoltageReference Input VoltageVoltage Range
47HDVCCO47, pins J3-43, J3-44user-max. 3.3V
48HDVCCO48, pins J3-15, J3-16user-max. 3.3V
64HPVCCO64, J4-58, J4-106userVREF_64, pin J4-88max. 1.8V
65HPVCCO65, J4-69, J4-105userVREF_65, pin J4-15max. 1.8V
66HPVCCO66, J1-90, J1-120userVREF_66, pin J1-108max. 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 1618: Range of MPSoC module's bank voltages

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Module VariantZynq Ultrascale+ MPSoCDDR4Zynq Ultrascale+ MPSoC Junction TemperatureOperating Temperature Range
TE0808-04-09EG-1EAXCZU9EG-1FFVC900E2GB0°C - 100°CExtended Temperature Range
TE0808-04-09EG-2IBXCZU9EG-2FFVC900I4GB-40°C - 100°CIndustrial Temperature Range

Table 1719: Differences between variants of Module TE0808-04

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