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| - typo correction in PLL_RST
- add pin on power rails table
- correction MGT Lane assignment
- correction MGT CLK assignmentDDR section
|
| 2021-03-11 | v.35 | Antti Lukats | - typo correction in PLL_RST
- add pin on power rails table
- correction MGT Lane assignment
- correction MGT CLK assignment
|
| v.30 | Martin Rohrmüller | - Corrected clock connection to J2
|
| v.29 | John Hartfiel | |
| v.27 | John Hartfiel | - typo correction SI5345 I2C address
|
| v.26 | John Hartfiel | - typo SI5348 B2B IOs + link correction
|
| v.24 | Ali Naseri | - updated B2B connector max. current rating per pin
|
| | John Hartfiel | |
| 2017-10-20 | v.21 | Ali Naseri | - Update links (pdf, documentation) to revision 4
- ES silicon note removed
|
| 2017-08-28 | v.15 | John Hartfiel | |
| 2017-08-28 | v.14 | Jan Kumann | - Block diagram changed.
- SPI flash section fixed.
- Few smaller improvements.
|
| 2017-08-15 | v.12 | Vitali Tsiukala | Changed signals count in the B2B connectors table |
| 2017-08-15 | | John Hartfiel, Ali Naseri | - PCB REV04 Initial release
- update boot mode section
|
| 2017-02-06 | v.1 | Jan Kumann | Initial document |