Versions Compared

Old Version 3

changes.mady.by.user John Hartfiel

Saved on

compared with

New Version 4

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

JTAG signals routed directly through the CPLD to FPGA12 pin pinheader. Access between CPLD and FPGA pinheader can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGApinheader).

UART

UART is routed through the CPLD.

...