Page History
...
| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | 2.5 | 6 | V | EN63A0QI / TPS82085SIL data sheet *Note: PG_PL will be pullup with this voltage |
| DCDCIN | 3.1 | 6 | V | TPS82085SIL / TPS51206PSQ data sheet |
| LP_DCDC | 2.5 | 3.6 | V | TPS82085SIL / TPS3106 data sheet |
| GT_DCDC | 2.5 | 6 | V | TPS82085SIL data sheet |
| PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
| PLL_3V3 | 3.14 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
| VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
...
| Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
| ||||||||||||||||||||||||||
| v.27 | John Hartfiel |
| |||||||||||||||||||||||||||
| v.26 | John Hartfiel |
| |||||||||||||||||||||||||||
| v.24 | Ali Naseri |
| |||||||||||||||||||||||||||
2017-11-13 | John Hartfiel |
| |||||||||||||||||||||||||||
| 2017-10-20 | v.21 | Ali Naseri |
| ||||||||||||||||||||||||||
| 2017-08-28 | v.15 | John Hartfiel |
| ||||||||||||||||||||||||||
| 2017-08-28 | v.14 | Jan Kumann |
| ||||||||||||||||||||||||||
| 2017-08-15 | v.12 | Vitali Tsiukala | Changed signals count in the B2B connectors table | ||||||||||||||||||||||||||
| 2017-08-15 | v.11 | John Hartfiel, Ali Naseri |
| ||||||||||||||||||||||||||
| 2017-02-06 | v.1 | Jan Kumann | Initial document |
...
Overview
Content Tools