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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.2
  • Changes Xilinx to AMD
ED

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Perihery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
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        repeatTableHeadersdefault
        sortByColumn1
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        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0808 is an industrial grade MPSoC SOM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC
    • Device: ZU6 / ZU9 / ZU15 1) 2)
    • Engine: CG / EG  1)
    • Speedgrade: -1 / -2  1)
    • Temperature Range: Extended / Industrial 1)
    • Package: FFVC900
  • RAM/Storage
    • 8 GByte DDR4 SDRAM 3)
    • 2 x 64 MByte Serial Flash 4)
    • EEPROM with MAC address
  • On Board
    • Oscillator
  • Interface
    • 4 x B2B Connector (ST5)
      • up to 204 PL IO

        • HP: 156
        • HD: 48
      • up to 65 PS MIO

      • 4 GTR
      • 16 GTH
      • I2C, JTAG, CONFIG
  • Power
    • 3.3 V power supply via B2B Connector needed 5).
  • Dimension
    • 76 mm x 52 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) without PCIe Core on PL, see XMP104
    3) Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    4) Please, take care of the possible assembly options.
    5) Dependent on the assembly option a higher input voltage may be possible

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTE0808 block diagram


Scroll Ignore

draw.io Diagram
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Image Modified


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titleTE0808 main components


Scroll Ignore

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Scroll Only

Image Modified


  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U4
  6. Clock Generator, U5
  7. Oscillator, U25, U32
  8. Done LED D1

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

DDR4 SDRAMnot programmed
Quad SPI Flashnot programmed
EEPROMnot programmed besides factory programmed MAC address
Programmable Clock Generatornot programmed


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
  • Table with all connectors and Designtor
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


Connectors

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Connector TypeDesignatorInterfaceIO CNTNotes
B2BJM1MGT PL12 x MGT (RX/TX)
B2BJM1HP52 SE / 24 DIFF
B2BJM2MGT PS2 x MGT CLK
B2BJM2CLK4 x DIFF CLKPLL
B2BJM2MGT PL4 x MGT (RX/TX)
B2BJM2MGT PS4 x MGT (RX/TX)
B2BJM2CFG1)1 x JTAG
B2BJM2CFG1)4 x MODE
B2BJM2CFG1)1 x I2CPLL, EEPROM
B2BJM2CFG1)34 CTRL/Status
B2BJM3HD48 SE / 24 DIFF
B2BJM3MGT PL3 x MGT CLK
B2BJM3CLKDIFF CLKPLL
B2BJM3MIO65 PS GPIO
B2BJM4HP104 SE / 48 DIFF

1) see Configuration and System Control Signals


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalNotes1)
TP1PWR_PL_OK

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.


Scroll Title
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Test PointSignalNotes
TP1PLL_SCLpulled-up to PS_1V8
TP2PLL_SDApulled-up to PS_1V8
TP3LP_DCDC
TP4DCDCIN
TP5GND
TP6TCK
TP7PL_DCIN
TP8GND
TP9GT_DCDC
TP10GND
TP11TDI
TP12TDO
TP13TMS
TP14PS_1V8
TP15No Net NameREF3312AIDCKT (U33) ouput voltage
TP16FP_0V85
TP17DDR_2V5
TP18DDR_PLL
TP19PL_VCCINT
TP20AUX_R
TP21AVTT_R
TP22AUX_L
TP24AVCC_R
TP26AVTT_L
TP28AVCC_L
TP30PS_PLL
TP31PS_AVTT
TP32LP_0V85
TP33PS_AUX
TP34PS_AVCC
TP36POR_Bpulled-up to PS_1V8


On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY



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Chip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2, U3, U9, U12SoC - PS

Quad SPI Flash

U7, U17SoC - PSBooting.

EEPROM

U4B2B - J2

Clock Generator

U5B2B - J2
SoC, - MGT

Oscillator

U25Clock Generator25 MHz

Oscillator

U32SoC - PS33.333333 MHz



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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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  • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
  • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)


Scroll Title
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titleController signal.

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Connector+Pin

Signal Name

Direction1)Description
JM2-77EN_PLL_PWRINEnable PLL power supply.
JM2-79EN_GT_LINEnable left GTH transceiver power-up.
JM2-80PG_PLL_1V8OUTSI_PLL_1V8 power rail powered-up.
JM2-81PLL_FINCINPLL Frequency incrementation.
JM2-82PG_PSGTOUTGTR transceivers powered-up.
JM2-83MRINManual reset.
JM2-84EN_PSGTINEnable GTR transceiver power-up.
JM2-85PLL_LOLnOUTLoss of lock status.
JM2-86ERR_STATUSOUTPS error status 2).
JM2-87PLL_SEL1INPLL clock selection.
JM2-88ERR_OUTOUTPS error indication 2).
JM2-89PLL_RSTINPLL reset.
JM2-90PLL_SCLINI2C clock. Pulled up to PS_1V8.
JM2-91PG_GT_ROUTRight GTH Transceivers powered-up.
JM2-92PLL_SDAIN/OUTI2C data. Pulled up to PS_1V8.
JM2-93PLL_SEL0INPLL clock selection.
JM2-94PLL_FDECINPLL Frequency decrementation.
JM2-95EN_GT_RINEnable right GTH transceiver power-up.
JM2-96SRST_BINSystem reset 2). Pulled-up to PS_1V8.
JM2-97PG_GT_LOUTLeft GTH Transceivers powered-up.
JM2-98INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
JM2-100PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
JM2-101EN_PLINEnable programable logic power-up.
JM2-102EN_FPDINEnable full-power domain power-up.
JM2-103 / JM2-105 / JM2-107 / JM2-109MODE3..0INBoot mode selection 2):
  • JTAG
  • QUAD-SPI (32 Bit)
  • SD1 (2.0)
  • eMMC (1.8 V)
  • SD1 LS (3.0)

Supported Modes depends also on used Carrier.

JM2-104PG_PLOUTProgrammable logic powered-up. Pulled-up to PL_DCIN.
JM2-106LP_GOODOUTLow-power domain powered-up. Pulled up to LP_DCDC.
JM2-108EN_LPDINEnable low-power domain power-up.
JM2-110PG_FPDOUTFull-power domain powered-up. Pulled-up to DCDCIN.
JM2-112EN_DDRINEnable DDR power-up.
JM2-114PG_DDROUTDDR power supply powered-up. Pulled-up to DCDCIN.
JM2-116DONEOUTPS done signal 2). Pulled-up to PS_1V8.
JM2-119 / JM2-121DX_P / DX_N-SoC temperatur sensing diode pins 2).
JM2-120 / JM2-122 /
JM2-124 / JM2-126
TCK / TDI / TDO / TMSSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

JM2-125PSBATTINPS RTC Battery supply voltage 2) 3).
JM2-127PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

2) See UG1085 for additional information.

3) See Recommended Operating Conditions.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

  • Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details


Power Rails

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List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power



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Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
VCCO_66JM1-90 / JM1-120IN
VREF_66JM1-108IN

PL_1V8

JM1-91 / JM1-121OUT
PL_DCINJM1-151 / JM1-153 / JM1-155 / JM1-157 / JM1-159IN
LP_DCDCJM2-138 / JM2-140 / JM2-142 / JM2-144IN
DCDCINJM2-153 / JM2-154 / JM2-155 / JM2-156 / JM2-157 / JM2-158 / JM2-159 / JM2-160IN
PS_1V8JM2-99 / JM3-147 / JM3-148OUT
PS_BATTJM2-125IN
DDR_1V2JM2-135OUT
VCCO_48JM3-15 / JM3-16IN
VCCO_47JM3-43 / JM3-44IN
PLL_3V3JM3-152IN
SI_PLL_1V8JM3-151OUT
GT_DCDCJM3-157 / JM3-158 / JM3-159 / JM3-160IN
VCCO_64JM4-58 / JM4-106IN
VREF_64JM4-88IN
VCCO_65JM4-69 / JM4-105IN
VREF_65JM4-15IN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Attention: PL usage is not completely independent of PS side. For PL usage it is necessary to enable PS low-power domain.

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SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
2Processing System (PS):

Procedure for PS starting.
2.1Low-power domain:Bring-up for low-power domain PS.
2.1.1LP_DCDC3.3 V (± 5 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_LPD--Low-power domain power enable.
2.1.3LP_GOOD-PU 3), LP_DCDCLow-power domain power good status.Module power-on sequencing for low-power domain finished.
2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
2.2.1DCDCIN3.3 V (± 5 %) 2)
Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_FPDDCDCIN-Full-power domain power enable.
2.2.3PG_FPD-PU 3), DCDCINFull-power domain power good status.Module power-on sequencing for full-power domain finished.
2.2.4EN_DDRDCDCIN-DDR memory power enable.
2.2.5PG_DDR-PU 3), DCDCINDDR memory power good status.Module power-on sequencing for DDR memory finished.

2.3

GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1EN_PSGTDCDCIN-GTR transceiver power enable.
2.3.2PG_PSGT--GTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
2Programmable Logic (PL)Procedure for PL starting.PL usage needs powered PS low-power domain.
2.1PL_DCIN3.3 V (± 5 %) 2)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2EN_PL-PU 3), PL_DCINProgrammable logic power enable.
2.3PG_PL-PU 3), PL_DCINProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 4)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
3.1GT_DCDC3.3 V (± 5 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.21)EN_PLL_PWR--PLL power enable.
3.21)PG_PLL_1V8--PLL power good status.
3.21)PLL_3V33.3 V (± 5 %)
PLL power supply
3.3EN_GT_L / EN_GT_RGT_DCDC-GTH / GTY left / right transceiver power enable.Transceivers on left / right side can be used independently.
3.4PG_GT_L / PG_GT_R--GTH / GTY transceiver power good status.
4MR

Manual ResetLow active release after all needed power domains are enabled. 

1) optional fpr MGT  Reference Clocks

2) Dependent on the assembly option a higher input voltage may be possible. 

3) On module

4) See DS925 for additional information.

Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings *)

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Power Rail Name/ Schematic NameDescriptionMinMaxUnit
LP_DCDCMicromodule Power-0.3004.0V
DCDCINMicromodule Power-0.3006.0V
GT_DCDCMicromodule Power-0.3006.0V
PL_DCINMicromodule Power-0.300

3.6

V
PLL_3V3PLL power supply-0.5003.8V
PS_BATTRTC / BBRAM-0.5002.000V
VCCO_47HD IO Bank power supply-0.5003.400V
VCCO_48HD IO Bank power supply-0.5003.400V
VCCO_64HP IO Bank power supply-0.5002.000V

VCCO_65

HP IO Bank power supply-0.5002.000V
VCCO_66HP IO Bank power supply-0.5002.000V
VREF_64Bank input reference voltage-0.5002.000V
VREF_65Bank input reference voltage-0.5002.000V
VREF_66Bank input reference voltage-0.5002.000V


*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


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ParameterMinMaxUnitsReference Document
LP_DCDC 1)3.1353.465V
DCDCIN 1)3.1353.465V
GT_DCDC 1)3.1353.465V
PL_DCIN 1)3.135

3.465

V
PLL_3V33.143.465V
PS_BATT1.2001.500VSee FPGA datasheet.
VCCO_471.1403.400VSee FPGA datasheet.
VCCO_481.1403.400VSee FPGA datasheet.
VCCO_640.9501.900VSee FPGA datasheet.

VCCO_65

0.9501.900VSee FPGA datasheet.
VCCO_660.9501.900VSee FPGA datasheet.
VREF_640.61.2VSee FPGA datasheet.
VREF_650.61.2VSee FPGA datasheet.
VREF_660.61.2VSee FPGA datasheet.

1) Higher values may possible. For more information consult schematic and according datasheets.


Physical Dimensions

  • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 1.6 mm (± 10 %).

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


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Trenz shop TE0808 overview page
English pageGerman page


Revision History

Hardware Revision History

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Set correct links to download  Carrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02



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DateRevisionChangesDocumentation Link
-05Second production siliconTE0808-05
-04First production siliconTE0808-04
-03Second ES production releaseTE0808-03
2016-03-0902First ES production releaseTE0808-02
-01Prototypes-


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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 Date

Revision

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  • Review and Public Update

2023-10-13

v.44

ED 

  • Updated to new TRM style

2022-09-13

v.41Vadim Yunitski
  • Updated PG_PL pull-up resistor requirements
2021-09-07V.39John Hartfiel
  • Correction Power section
2021-05-17v.37John Hartfiel
  • typo correction in DDR section
2021-03-11v.35Antti Lukats
  • typo correction in PLL_RST
  • add pin on power rails table
  • correction MGT Lane assignment
  • correction MGT CLK assignment

2019-01-27

v.30Martin Rohrmüller
  • Corrected clock connection to J2

2018-11-20

v.29

John Hartfiel
  • Notes for power supply

2018-08-27

v.27John Hartfiel
  • typo correction SI5345 I2C address

2028-06-28

v.26John Hartfiel
  • typo SI5348 B2B IOs + link correction

2017-11-13

v.24Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13


v.22


John Hartfiel
  • rework B2B section
2017-10-20

v.21

Ali Naseri
  • Update links (pdf, documentation) to revision 4
  • ES silicon note removed
2017-08-28
v.15
John Hartfiel
  • Update section: Variants Currently In Production

2017-08-28v.14Jan Kumann
  • Block diagram changed.
  • SPI flash section fixed.
  • Few smaller improvements.
2017-08-15v.12Vitali TsiukalaChanged signals count in the B2B connectors table
2017-08-15

v.11

John Hartfiel, Ali Naseri
  • PCB REV04 Initial release
  • update boot mode section
2017-02-06v.1Jan KumannInitial document

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Disclaimer

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IN:Legal Notices
IN:Legal Notices



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