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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Perihery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0813 is an industrial grade MPSoC SOM integrating a Xilinx Zynq UltraScale+, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections.
All this in a compact 5.2 cm x 7.6 cm form factor, at the most competitive price.
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
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- SoC
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 1)
- Engine: CG / EG / EV 1)
- Speedgrade: -1 / -2 1)
- Temperature Range: Extended / Industrial 1)
- Package: SFVC784
- RAM/Storage
- 4 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- EEPROM with MAC address
- On Board
- Interface
- 4 x B2B Connector (ADM6)
up to 204 PL IO up to 65 PS MIO - 4 GTR
- 4 GTH (with ZU4 and higher)
- JTAG
- Power
- 3 V ... 5 V power supply via B2B Connector needed.
- Dimension
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. 2) Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s. 3) Please, take care of the possible assembly options. 4) Please, take care of the possible assembly options.
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TExxxx block diagram |
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draw.io Diagram |
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border | true |
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diagramName | TE0813_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 562 |
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revision | 5 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TExxxx main components |
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draw.io Diagram |
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border | true |
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diagramName | Figure_OV_MC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 742 |
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revision | 4 |
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Scroll Only |
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- SoC, U1
- DDR4, U2, U3, U9, U12
- Quad SPI Flash, U7, U17
- Connector, JM1, JM2, JM3, JM4
- EEPROM, U28
- Clock Generator, U5
- Oscillator, U6, U32
- Power Supply, U4, U8, U10, U11, U13 ... U16, U18 ... U24, U26, U27, U29 ...U31, U33, U34, U41
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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DDR4 SDRAM | not programmed |
| Quad SPI Flash | not programmed |
| EEPROM | not programmed besides factory programmed MAC address |
| Programmable Clock Generator | not programmed |
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Signals, Interfaces and Pins
Connectors
Scroll Title |
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator | Interface | IO CNT 1) | Notes |
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B2B | JM1 | MGT PL | 4 x MGT (RX/TX) |
| B2B | JM1 | HP | 52 SE / 24 DIFF |
| B2B | JM2 | MGT PS | 2 x MGT CLK |
| B2B | JM2 | MGT PS | 4 x MGT (RX/TX) |
| B2B | JM2 | CFG | JTAG |
| B2B | JM2 | CFG | MODE |
| B2B | JM3 | HD | 48 SE / 24 DIFF |
| B2B | JM3 | MGT PL | MGT CLK |
| B2B | JM3 | MIO | 65 GPIO |
| B2B | JM4 | HD | 104 SE / 48 DIFF |
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1) IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs |
Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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Scroll Title |
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes1) |
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TP1 | PLL_SCL | pulled-up to PS_1V8 | TP2 | PLL_SDA | pulled-up to PS_1V8 | TP5 | GND |
| TP6 | PL_1V8 |
| TP7 | GND |
| TP8 | GND |
| TP9 | PL_VCCINT_IO |
| TP10 | GND |
| TP11 | PL_VCCINT |
| TP12 | PL_VCU_0V9 |
| TP13 | FP_0V85 |
| TP14 | PS_1V8 |
| TP15 | GND |
| TP16 | DDR_2V5 |
| TP17 | DDR_PLL |
| TP18 | DDR_1V2 |
| TP20 | MGTAVTT |
| TP21 | VTT |
| TP22 | PL_GT_1V05 |
| TP23 | VREFA |
| TP24 | MGTVCCAUX |
| TP25 | MGTAVCC |
| TP27 | PS_PLL |
| TP28 | PS_AVTT |
| TP29 | LP_0V85 |
| TP30 | PS_AUX |
| TP31 | PS_AVCC |
| TP34 | POR_B | pulled-up to PS_1V8 |
1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS |
| Quad SPI Flash | U7, U17 | SoC - PS | Booting. | EEPROM | U28 | B2B - J2 |
| Clock Generator | U5 | SoC, B2B |
| Oscillator | U6 | Clock Generator | 25 MHz | Oscillator | U32 | SoC | 33.333333 MHz |
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Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Scroll Title |
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector+Pin | Signal Name | Direction1) | Description |
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JM1.A45 | POR_OVERRIDE | IN | Override power-on reset delay. | JM2.A31 | ERR_OUT | OUT | PS error indication. | JM2.A34 | ERR_STATUS | OUT | PS error status. | JM2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN | JM2.A36 | PLL_SCL | IN | I2C clock | JM2.A37 | PLL_SDA | IN/OUT | I2C data | JM2.A40 | PG_VCU | OUT | Programmable logic powered-up. | JM2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. | JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 | JM2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. | JM2.B30 | PROG_B | IN/OUT | Power-on reset. Pulled-up to PS_1V8. | JM2.B33 | SRST_B | IN | System reset. Pulled-up to PS_1V8. | JM2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR. Pulled-up to PS_1V8. | JM2.B37 | PG_PL | OUT | VCU powered-up. | JM2.B38 | EN_FPD | IN | Enable full-power domain power-up. | JM2,B41 | PG_FPD | OUT | Full-power domain powered-up. | JM2.B45 | PG_DDR | OUT | DDR power supply powered-up. | JM2.B46 | DONE | OUT | PS done signal. Pulled-up to PS_1V8. | JM2.B47 | EN_DDR | IN | Enable DDR power-up. | JM2.C31 | MR | IN | Manual reset. | JM2.C35 | EN_PL | IN | Enable programable logic power-up. | JM2.C36 | EN_GT_R | IN | Enable GTH/GTY transceiver power-up. | JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47 | MODE3..0 | IN | ...... |
1) Direction: - IN (C2M): Carrier to Module, means it's an input : Input from the point of view of this board.
- OUT (M2C): Module to Carrier, means it's output : Output from the point of view of this board.
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Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
Page properties |
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power
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Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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Recommended Power up Sequencing
Page properties |
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List baseboard design hints for final baseboard development. |
Scroll Title |
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Technical Specifications
Page properties |
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
Scroll Title |
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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| °C |
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*) Stresses beyond those listed under TE0813 TRM (more or less equal to TE0803 but other connectors) may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under TE0813 TRM (more or less equal to TE0803 but other connectors). Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
Scroll Title |
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| °C | See ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
Scroll Title |
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Currently Offered Variants
Scroll Title |
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Figure_RV_HRN |
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title-alignment | center |
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title | Board hardware revision number. |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Scroll Title |
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title-alignment | center |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| - <add TRM change list here>
| -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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