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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Perihery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial/extended grade ... module ... based on Xilinx/Intel...
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
Key Features
Excerpt |
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- SoC/FPGA/Module
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
Note |
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
Note |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TExxxx block diagram |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Scroll Title |
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TExxxx main components |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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- ...
- ...
- ...
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash |
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| EEPROM |
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| System Controller CPLD |
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| DDR4 SDRAM |
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| eMMC |
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| Programmable Clock Generator |
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Configuration Signals, Interfaces and Pins
Connectors
Scroll Title |
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anchor | Table_OVSIP_CNTRLC |
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title-alignment | center |
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title | Controller signal.Board Connectors |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| NameB2B/DirectionDescriptionBoot ModeEnable | Reset | JTAGSEL | PGOOD | ... | |
Signals, Interfaces and Pins
Test Points
B2B SoC/FPGA IOs
B2B JTAG Interface
B2B ETH Interface
B2B USB Interface
SD Card Connector
SMA Connector
MIO
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Note |
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MIO section only for SoC devices with dedicated MIO, otherwhise remove this section |
MIO Pins
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Only for SoC Modules(Xilinx MIO, for Intel and MicroChip SoC please change MIO to syntax of the manufacturer). you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
MIO Pins are only for SoC like Zynq, U+Zynq and Versal, for other FPGA modules remove this chapter
Example:
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes1) |
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TP1 |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
Test Points
Page properties |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 | Scroll Title |
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points InformationOn board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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TP2 | TP3 | TP4 | TP5 | TP6 | TP7 | TP8 | TP9 | TP10 |
On-board PeripheralsConfiguration and System Control Signals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: #ClockSources, #CPLD, #QuadSPIFlash |
- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Scroll Title |
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Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripheralsController signal. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Page properties |
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Connector+Pin | Signal Name | Direction1) | Description |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals |
Power and Power-On Sequence
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| In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power ConsumptionEnter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power
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Scroll Title |
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anchor | Table_PWR_PCPR |
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title-alignment | center |
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title | Power ConsumptionModule power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Input Rail Name/ Schematic Name | Connector + Pin |
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Typical Current | VIN | TBD* | |
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title-alignment | center |
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title | Power Distribution |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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Recommended Power up Sequencing
Page properties |
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List baseboard design hints for final baseboard development. |
Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title-alignment | center |
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title | Power SequencyBaseboard Design Hints |
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ignore |
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Voltage Monitor Circuit
Scroll Title |
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anchor | Figure_PWR_VMC |
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title-alignment | center |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
tablelayout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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Board to Board Connectors
Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Technical Specifications
Page properties |
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Scroll Title |
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anchor | Table_PWRTS_BVAMR |
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title-alignment | center |
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title | Zynq SoC bank voltages.PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
| Power Rail Name/ Schematic Name |
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VoltageNotes | |
Board to Board Connectors Page properties |
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This section is optional and only for modules.*) Stresses beyond those listed under TE0813 TRM (more or less equal to TE0803 but other connectors) may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under TE0813 TRM (more or less equal to TE0803 but other connectors). Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors Include Page |
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PD:6 x 6 SoM LSHM B2B Connectors | PD:6 x 6 SoM LSHM B2B Connectors | Technical Specifications
Absolute Maximum Ratings
Scroll Title |
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anchor | Table_TS_AMR |
---|
title-alignment | center |
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title | PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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V | V | V | V | V | V | V | V | °CRecommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
Scroll Title |
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| °C | See ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
Scroll Title |
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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|
Scroll Ignore |
---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Currently Offered Variants
Scroll Title |
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Figure_RV_HRN |
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title-alignment | center |
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title | Board hardware revision number. |
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|
Scroll Ignore |
---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Scroll Title |
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title-alignment | center |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| - <add TRM change list here>
| -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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| |
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Disclaimer
Include Page |
---|
| IN:Legal Notices |
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| IN:Legal Notices |
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|