Page History

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Scroll Title
      anchor Figure_xyz title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables

      • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

    • 
      

      Scroll Title
      anchor Table_xyz title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 2021.2.1

• PetaLinux

• SD

• FMeter

• ETH on CR00200 (J11 on TEB0707-02)

• Modified FSBL for SI5338 programming

Notes :

• add every update file on the download

• add design changes on description

Notes :

• add known Design issues and general notes for the current revision

• do not delete known issue, add fixed version time stamp if  issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of hardware which was used to generate the design

• mark the module and carrier board, which was used tested with an ^*

^*used as reference

^*used as reference

^*used as reference

Notes :

• content of the zip file

Notes :

• prebuilt files

• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title-alignment center title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Important set new Vivado version link on every Design update of new vivado version!

• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Notes :

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequency...
      

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

#SI5338
set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property PACKAGE_PIN C3 [get_ports {SI5338_CLK3_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK3_D_clk_p[0]}]


#CPLD
set_property PACKAGE_PIN B1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN C1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]


#Ethernet
#IO Placement
set_property PACKAGE_PIN R7 [get_ports {emio_tri_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {emio_tri_io[0]}]

set_property PACKAGE_PIN T7 [get_ports {CR00200_Phy_INTn}]
set_property IOSTANDARD LVCMOS18 [get_ports {CR00200_Phy_INTn}]

set_property PACKAGE_PIN L3 [get_ports {CR00200_Phy_CLK125}]
set_property IOSTANDARD LVCMOS18 [get_ports {CR00200_Phy_CLK125}]

#CR00200 --> TEB0707 J11 --> TE0821
set_property PACKAGE_PIN N9 [get_ports {ETH2_RGMII_txc}]
set_property PACKAGE_PIN N8 [get_ports {ETH2_RGMII_tx_ctl}]
set_property PACKAGE_PIN M8 [get_ports {ETH2_RGMII_td[0]}]
set_property PACKAGE_PIN L8 [get_ports {ETH2_RGMII_td[1]}]
set_property PACKAGE_PIN K7 [get_ports {ETH2_RGMII_td[2]}]
set_property PACKAGE_PIN K8 [get_ports {ETH2_RGMII_td[3]}]
set_property PACKAGE_PIN K4 [get_ports {ETH2_RGMII_rxc}]
set_property PACKAGE_PIN K3 [get_ports {ETH2_RGMII_rx_ctl}]
set_property PACKAGE_PIN M6 [get_ports {ETH2_RGMII_rd[0]}]
set_property PACKAGE_PIN L5 [get_ports {ETH2_RGMII_rd[1]}]
set_property PACKAGE_PIN P7 [get_ports {ETH2_RGMII_rd[2]}]
set_property PACKAGE_PIN P6 [get_ports {ETH2_RGMII_rd[3]}]

set_property PACKAGE_PIN Y8 [get_ports {ETH_MDIO_mdc}]
set_property PACKAGE_PIN W8 [get_ports {ETH_MDIO_mdio_io}]

set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RGMII_*}]
set_property IOSTANDARD LVCMOS18 [get_ports {ETH_MDIO_*}]

set_property PULLTYPE PULLUP [get_ports {ETH2_RGMII_*}]
set_property PULLTYPE PULLUP [get_ports {ETH_MDIO_*}]

#set_property slew FAST [get_ports {ETH2_RGMII_*}]
#set_property slew FAST [get_ports {ETH_MDIO_*}]


# Clock Period Constraints
create_clock -period 8.000 -name ETH2_RGMII_rxc -add [get_ports ETH2_RGMII_rxc]

## Use these constraints to modify output delay on RGMII signals if 2ns delay is added by external PHY
#set_output_delay -clock [get_clocks ETH2_RGMII_txc] -max -1.0 [get_ports {ETH2_RGMII_td[*] ETH2_RGMII_txc}]
#set_output_delay -clock [get_clocks ETH2_RGMII_txc] -min -2.6 [get_ports {ETH2_RGMII_td[*] ETH2_RGMII_txc}] -add_delay
#set_output_delay -clock [get_clocks ETH2_RGMII_txc] -clock_fall -max -1.0 [get_ports {ETH2_RGMII_td[*] ETH2_RGMII_txc}] 
#set_output_delay -clock [get_clocks ETH2_RGMII_txc] -clock_fall -min -2.6 [get_ports {ETH2_RGMII_td[*] ETH2_RGMII_txc}]

#clock setting
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports ETH2_RGMII_td[1]]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports ETH_MDIO_mdio_io]


##clock setting
##set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets zusys_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/rgmii_rxc_ibuf_i/O]
#set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports ETH2_RGMII_td[1]]


##False path constraints to async inputs coming directly to synchronizer
#set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }]
#set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/SYNC_*/data_sync* }] -filter { name =~ *D }]
#set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]

##False path constraints from Control Register outputs 
#set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/DUPLEX_MODE_REG*/C }]
#set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/SPEED_SELECTION_REG*/C }]

## constraint valid if parameter C_EXTERNAL_CLOCK = 0
#set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE0}]
#set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S0}]
#set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/CE1}]
#set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk/S1}]

## constraint valid if parameter C_EXTERNAL_CLOCK = 0 and clock skew on TXC is through MMCM
#set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE0}]
#set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S0}]
#set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/CE1}]
#set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_90_clk/S1}]

##These constraints are for non-Versal devices
##To Adjust GMII Rx Input Setup/Hold Timing
#set_property IDELAY_VALUE 16 [get_cells *delay_rgmii_rx_ctl]
#set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}]
#set_property IODELAY_GROUP gpr1 [get_cells *delay_rgmii_rx_ctl]
#set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}]
#set_property IODELAY_GROUP gpr1 [get_cells *idelayctrl]

#set_property slew FAST [get_ports [list {ETH2_RGMII_td[3]} {ETH2_RGMII_td[2]} {ETH2_RGMII_td[1]} {ETH2_RGMII_td[0]} ETH2_RGMII_txc ETH2_RGMII_tx_ctl]]

#clock setting
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets zusys_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/rgmii_rxc_ibuf_i/O]

Note:

• optional chapter separate

• sections for different apps

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2021.2 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c (for hooks and board)

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Note:

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

#include <configs/xilinx_zynqmp.h>
#no changes

/include/ "system-conf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};

/*------------------------- QSPI ------------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        //compatible = "flash name, "micron,m25p80";
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/*----------------------- SD1 sd2.0 -----------------------*/
&sdhci1 {
    disable-wp;
    no-1-8-v;
};

/*------------------------- ETH PHY -----------------------*/
/delete-node/ &psu_ethernet_2_mdio;
&gem2 { 
    phy-handle = <&phy1_gem2>;
    phy-mode = "rgmii-id";
    status = "okay";
    
    reset-names = "ETH_RST"; 
    reset-gpios = <&gpio 78 GPIO_ACTIVE_LOW>;
    
    phy1_gem2: ethernet-phy@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };

    rgmii_0: rgmii_0@4 {
        phy-handle = <&phy1_gem2>;
        compatible = "xlnx,gmii-to-rgmii-1.0";
        reg = <4>;
    };
};



/*----------------------- USB 2.0 only --------------------*/
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
    snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
    
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};

/*---------------------------- I2C ------------------------*/
&i2c0 {
  eeprom: eeprom@50 {
     compatible = "microchip,24aa025", "atmel,24c02";
     reg = <0x50>;
  };
};
    

Note:

• Add description for other Software, for example SI CLK Builder ...

• SI5338 and SI5345 also Link to:

  • Si5345

  • Si5338

• Note this list must be only updated, if the document is online on public doc!

• It's semi automatically, so do following

  • Add new row below first

  • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports