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The TE0722 is configured to boot from flash with JTAG in cascade mode. If you configure the TE0722 Flash with wrong Boot.bin (for ex. you use Xilinx default or wrong FSBL. Or you insert additional applications file into the boot.bin without necessary workarounds), the Zynq - PS is running into a state, in which the FPGA and the Flash is not accessible via JTAG.This workaround set the FPGA in JTAG independent mode on startup to erase the corrupt flash content.
| Note |
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The Xilinx tools do not handle DDR-Less Design correctly, to get around this "bug" manual modifications are necessary, see DDR less ZYNQ Design. It should be fixed or make a little bit confortable by Xilinx but until Vivado 2016.2 it's not done. |
Procedure
For this case, you can try the following steps without guarantee for success:
- Close all Xilinx Programs.
- Power off TE0722
- Bridge S25FL127S Pin 7 temporary with GND to set Boot Mode to independent JTAG (See picture xxx).
- Power on TE0722
- Open SDK
- Disconnect you GND bridge to Pin 7
- (optional) Try to get access to the FPGA with SDK Debugger (Is this not possible, flash programming is also not possible)
- Try to program Flash with valid Boot.Bin, if programming failed try again from step 1.
GND-Bridge to S25FL127S Pin 7
Pin 7 is connected with Pullup-Resistor to 3.3V, to set FPGA in Quad-SPI Mode. To Short this Pin with GND enable JTAG Bode Mode only.
Connect Pin 7 to Pin 4 (GND) only temporary for startup procedure. After startup, Pin 7 trace is used to program the Flash. So you must disconnect your GND-bridge.
References
- Zynq-7000 All Programmable SoC - Technical Reference Manual (UG585):Page 167-Section 6.25 Boot Mode Pin Settings
- TE0722 Schematics:TE0722 Download Page
- S25FL127SABMFV10 Datasheet
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