Page History
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Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
EFUSE USER | Not programmed | - |
EFUSE Security | Not programmed | - |
Interfaces and Pins
Board to Board (B2B) I/O's
I/O signals connected to the SoC's I/O bank and B2B connector:
Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
13 | HR | JM1 | 48 | User | - |
34 | HR/HP | JM2 | 18 | User | 1.8V max with XC7Z030! |
35 | HR/HP | JM2 | 50 | User | 1.8V max with XC7Z030! |
34 | HR/HP | JM3 | 16 | User | 1.8V max with XC7Z030! |
500 | MIO | JM1 | 8 | 3.3V | - |
501 | MIO | JM1 | 6 | 1.8V | - |
112 | GT | JM3 | 4 Lanes | N/A | - |
112 | GT CLK | JM3 | One Differential Input | N/A | NB! AC coupling capacitors on baseboard required. |
For detailed information about the pin out, please refer to the Master Pinout Table.
Default MIO Mapping
MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | |
---|---|---|---|---|---|---|---|---|
0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | |
1 | QSPI0 | - | SPI Flash-CS | 28..39 | USB0 | - | ULPI | |
2 | QSPI0 | - | SPI Flash-DQ0 | 40 | SDIO0 | JM1-27 | B2B | |
3 | QSPI0 | - | SPI Flash-DQ1 | 41 | SDIO0 | JM1-25 | B2B | |
4 | QSPI0 | - | SPI Flash-DQ2 | 42 | SDIO0 | JM1-23 | B2B | |
5 | QSPI0 | - | SPI Flash-DQ3 | 43 | SDIO0 | JM1-21 | B2B | |
6 | QSPI0 | - | SPI Flash-SCK | 44 | SDIO0 | JM1-19 | B2B | |
7 | GPIO | - | Green LED D4 | 45 | SDIO0 | JM1-17 | B2B | |
8 | QSPI0 | - | SPI Flash-SCKFB | 46 | GPIO | - | Ethernet PHY LED2 INTn Signal. | |
9 | JM1-91 | B2B | 47 | GPIO | - | RTC Interrupt | ||
10 | JM1-95 | B2B | 48 | I2C1 | - | SCL on-board I2C | ||
11 | JM1-93 | B2B | 49 | I2C1 | - | SDA on-board I2C | ||
12 | JM1-99 | B2B | 50 | GPIO | - | ETH0 Reset | ||
13 | JM1-97 | B2B | 51 | GPIO | - | USB Reset | ||
14 | UART0 | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
15 | UART0 | JM1-85 | B2B | 53 | ETH0 | - | MDIO |
Gigabit Ethernet
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an onboard 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
Ethernet PHY connection
PHY Pin | ZYNQ PS | ZYNQ PL | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
LED2/Interrupt | MIO46 | - | - |
CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
RESETn | MIO50 | - | - |
RGMII | MIO16..MIO27 | - | - |
SGMII | - | - | on B2B. |
MDI | - | - | on B2B. |
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an onboard 52MHz oscillator (U15).
USB PHY connection
PHY Pin | ZYNQ Pin | B2B Name | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
REFCLK | - | - | 52MHz from on board oscillator (U15). |
REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz. |
RESETB | MIO51 | - | Active low reset. |
CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
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On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
I2C Device | I2C Adress | Notes |
---|---|---|
EEPROM | 0x50 | |
RTC | 0x6F | |
Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
---|---|
TCK | JM2-99 |
TDI | JM2-95 |
TDO | JM2-97 |
TMS | JM2-93 |
Note |
---|
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | Default Configuration |
---|---|---|---|
EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
NOSEQ | - | - | No function. |
RESIN | Input | Reset | Active low reset, gated to POR_B. |
JTAGEN | Input | JTAG Select | Low for normal operation. |
Boot Mode Pin
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
MODE Signal State | Boot Mode |
---|---|
high or open | SD Card |
low or ground | QSPI |
LED's
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Onboard Peripherals
Processing System (PS) Peripherals
Name | IC | ID | PS7 | MIO | Notes |
---|---|---|---|---|---|
SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | |
EEPROM I2C | 24AA025E48 | U19 | I2C1 | MIO48, MIO49 | EEPROM for MAC Address. |
RTC | ISL2020 | U16 | I2C1 | MIO48, MIO49 | Temperature compensated RTC. |
RTC Interrupt | ISL2020 | U16 | GPIO | MIO47 | Real Time Clock Interrupt. |
Clock PLL | Si5338 | U10 | I2C1 | MIO48, MIO49 | Low jitter phase locked loop. |
LED | - | D4 | GPIO | MIO7 | |
USB | USB3320 | U6 | USB0 | MIO28..MIO39 | |
USB Reset | - | - | GPIO | MIO51 | |
Ethernet | 88E1512 | U7 | ETH0 | MIO16..MIO27 | |
Ethernet Reset | - | - | GPIO | MIO50 |
Clocking
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
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There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
I/O | Default Frequency | Notes |
---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | 125MHz | Bank 34 clock input. |
CLK3B | - | Not used, disabled. |
MAC-Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
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Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
Power Input Pin | Max Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
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See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
Bank Voltages
Bank | Voltage | TE0715-xx-15 | TE0715-xx-30 |
---|---|---|---|
500 MIO0 | 3.3V | - | - |
501 MIO1 | 1.8V | - | - |
502 DDR | 1.5V | - | - |
0 Config | 3.3V | - | - |
13 HR | User | Max 3.3V | Max 3.3V |
34 HR/HP | User | Max 3.3V | Max 1.8V |
35 HR/HP | User | Max 3.3V | Max 1.8V |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
VBat supply voltage | -1 | 6.0 | V | - |
PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | Co | - |
Storage temperature without the ISL12020MIRZ | -55 | +100 | Co | - |
Note |
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Assembly variants for higher storage temperature range are available on request. |
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Power Rails
Voltages on B2B- Connectors | B2B JM1-Pin | B2B JM2-Pin | B2B JM3-Pin | Input/ Output | Note |
---|---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | - | Input | supply voltage |
3.3VIN | 13, 15 | - | - | Input | supply voltage |
VCCIO13 | 9, 11 | - | - | Input | high range bank voltage |
VCCIO34 | - | 5 | - | Input | TE0715-xx-15: high range bank voltage, TE0715-xx-30: high performance bank voltage |
VCCIO35 | - | 7, 9 | - | Input | TE0715-xx-15: high range bank voltage, TE0715-xx-30: high performance bank voltage |
VBAT_IN | 79 | - | - | Input | RTC battery-buffer voltage |
3.3V | - | 10, 12, 91 | - | Output | intern 3,3V Voltage-Level |
1.8V | 39 | - | - | Output | intern 1,8V Voltage-Level |
1.5V | - | 19 | - | Output | intern 1,5V Voltage-Level |
USB_VBUS | - | - | Pin 55 | Input | external 5V USB-Bus Power-Supply, if needed |
GND | F1, F2 | F1, F2 | F1, F2 | - | - |
Bank Voltages
Bank | Voltage | TE0715-xx-15 | TE0715-xx-30 |
---|---|---|---|
500 MIO0 | 3.3V | - | - |
501 MIO1 | 1.8V | - | - |
502 DDR | 1.5V | - | - |
0 Config | 3.3V | - | - |
13 HR | User | 3.3V capable | 3.3V capable |
34 HR/HP | User | 3.3V capable | 1.8V capable |
35 HR/HP | User | 3.3V capable | 1.8V capable |
Technical Specifications
Recommended Operating Conditions
Parameter | Min | Max | Units | Notes | Reference Document |
---|---|---|---|---|---|
VIN supply voltage | 2.5 | 5.5 | V | ||
3.3VIN supply voltage | 3.135 | 3.465 | V | ||
VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
VBat supply voltage | -1 | 6.0 | V | - |
PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | °C | - |
Storage temperature without the ISL12020MIRZ | -55 | +100 | °C | - |
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Note |
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Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers
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8.8 g - Set of bolts and nuts
Document Change History
Date | Rrevision | Contributors | Description |
---|---|---|---|
2016-06-28 | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pinout Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. | ||
2016-04-27 | V33 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis | Added the table "Recommended Operating Conditions" Storage Temperature edited. |
2016-03-31 | V10 | Philipp Bernhardt, Antti Lukats, Thorsten Trenz | Initial version. |
Hardware Revision History
Date | Revision | Notes | PCN |
---|---|---|---|
- | 01 | Prototypes | |
- | 02 | Prototypes | |
- | 03 | First production release | |
2016-06-21 | 04 | Second production release | Click to see PCN |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
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