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RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.
| RGPIO Pin to FPGA | Value |
|---|
| 0 | MIO10 |
| 1 | MIO11 |
| 2 | MIO12 |
| 3 | MIO13 |
| 4 | MIO14 |
| 5 | MIO15 |
| 6-9 | USR0-USR3 (S4-1...S4-4) |
| 10-11 | CM0-CM1(S3-M1...S3-M2) |
| 12 | SD_WP |
| 13 | SD_DETECT |
| 14 | USB_OC |
| 15 | POK_FMC |
| 16 | S1 |
| 17 | PGOOD |
| 18 | NOSEQ |
| 19 | VID0 |
| 20 | X6 |
| 21 | Y6 |
| 22 | VID1 |
| 23 | VID2 |
| 24-27 | reserved |
| 28-31 | Interface detection |
| RGPIO Pin from FPGA | Value |
|---|---|
| 0-7 | LED 1-7 |
| 08-23 | unused |
| 24-27 | reserved |
| 28-31 | Interface detection |
LED
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LED
| LED | Description |
|---|---|
| ULED1 | not external reset / RGPIO(0), when FPGA Interface is detected |
| ULED2 | (M1=off,M2=off) / RGPIO(1), when FPGA Interface is detected |
| ULED3 | Module UART0.RX / RGPIO(2), when FPGA Interface is detected |
| ULED4 | Module UART0.TX / RGPIO(3), when FPGA Interface is detected |
| ULED5 | SD_DETECT / RGPIO(4), when FPGA Interface is detected |
| ULED6 | (M1=on,M2=off) / RGPIO(5), when FPGA Interface is detected |
| ULED7 | X6 / RGPIO(6), when FPGA Interface is detected |
| ULED8 | Y6 / RGPIO(7), when FPGA Interface is detected |
UART
| To | From | Description |
|---|---|---|
| MIO14 | BDBUS0 | Module UART0.RX |
| BDBUS1 | MIO15 | Module UART0.TX |
Appx. A: Change History and Legal Notices
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Overview
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