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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0741

The TE0741 board module is available in four different logic densities (70T, 160T, 325T and 410T). The 70T and 160T devices can be programmed with the free Xilinx Vivado WebPACK software. Further information on about the Kintex-7 FPGA can be found in the Xilinx  document document 7 Series FPGAs FPGA's Overview (DS180).

Block Diagram

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Figure 1: TE0741 Block Diagram.

Main Components

Figure 2: TE0741 (REV 02).

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• Industrial-grade Xilinx Kintex-7 FPGA module (70T*, 160T*, 325T, 410T)
  * Device supported by the free Xilinx Vivado WebPACK toolsoftware.
• 256 Mbit (32 MbyteMByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect (Bus Width x4))
• 8 GTX transceivers
• FPGA configuration through:
  • JTAG (B2B connector)
  • SPI Flash memory
• 25 MHz low jitter oscillator with shutdown control
• Programmable quad PLL-clock generator
• On-board high-efficiency DC-DC converters
  • GTX voltage regulators with control enable
  • Core voltage regulator: 20 A 20A (2 x Enpirion DC/DC regulators with load-sharing)
  • Supply voltages: either 3.3 V 3V or 3.3 V 3V and 5 V5V
• Plug-on module with two 100-pin and one 60-pin high-speed hermaphroditic stacking strips
• Up to 144 (94 for 70T) FPGA I/O  pins available on B2B strips (up to 65 LVDS pairs possible)
• 2 user LEDsLED's, 1 DONE FPGA pin LED, 1 System Controller status LED
• System management and power sequencing
• AES bit-stream encryption
• eFUSE bit-stream encryption
• Evenly spread supply pins for good signal integrity
• Assembly options for cost or performance optimization available on request

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Table 1: Initial delivery state.

Signals, Interfaces and Pins

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I/O signals connected to the FPGA's I/O banks and B2B connector:

 Table 2:  Voltage ranges and pin-outs of available logic banks of the FPGA.

Please use Master Pinout Pin-out Table table as primary reference for the pin mapping information.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table 4: Pin-description of System Controller CPLD

LEDs

On the SoM TE0741 there is a total of 4 LEDS available. Two LEDs are status LEDs, the other ones can an be freely used by customer designs. The user LEDs are routed to the FPGA by the nets with the schematic-names 'LED1' and 'LED2'.

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LED's

There are four LED's available on TE0741 SoM. Two status LED's (D3 and D4) and two user configurable LED's (D1 and D2).

Table 5: Description of the on board LEDsLED's.

Note: if FPGA logic toggles DONE pin (to control D3) then D4 will toggle at random, as changing value on DONE will change the blink frequency of D4.

Clocking

To enable the PLL (phase-locked loop) clock generator Si5338A (U2), CLK_EN-signal (bank 14, pin C26) must be set to high, to activate the 25 MHz reference clock SiT8208AI (U3). The GTX reference clocks 0 and 2 have to be provided by the user on B2B connector JM3.

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A 25 MHz oscillator is connected to pin IN3 and is used to generate the output clocks. The oscillator has its enable pin connected to an FPGA pin (CLK_EN). Driving the FPGA pin low will disable the oscillator output, or setting it high will enable it. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTX banks. It is possible to use the clocks connected to the GTX bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

The default frequency of each clock at start up is detailed in the table 7.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA to exercise the utilize I2C bus with the correct datacorrectly.

Figure 3: Clock Generator block diagram.

Table 7: Pin description of PLL clock generator Si5338A.

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MByte Quad SPI Flash Memory

An SPI flash memory S25FL256SAGBHI20 (U4) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate will be dependent depends on the bus width and clock frequency.

GTX Transceivers

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To enable the voltage supply for the GTX transceivers, namely the Enpirion EP53F8QI voltage regulators U6 and U16, which serve the voltages MGTAVCC (1.0 V) and MGTAVTT (1.2 V), the signal EN_MGT (bank 14, pin H22) have to be set to high. The voltage regulators than return the will indicate "Power OK" -with signals PG_MGT_1V and PG_MGT_1V2, when the voltage regulators reaches reaching stable state.

Figure 4: GTX Transceiver block diagram.

System Controller

The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Setting input signal RESIN low will also reset the FPGA. This signal can be driven from the user’s PCB via the board connector.

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Figure 5: System Controller block diagram.

Power and Power-On Sequence

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A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3V is routed through a power switch to generate the output 3VIN will be switched to the internal 3.3V . This voltage level after the FPGA 1.0V supply is stable. Than this power supply will not be available until the power sequencing has completedon the B2B connector pins.

The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are detailed below.

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Figure 6: Connections between the on-board DCDC and LDO regulators.

Power Rails

Table 9: Power rails of SoM on B2B connectors.

Bank Voltages

Table 10: Range of FPGA's bank voltages.

See the Kintex-7 datasheet (DS182) for the allowable voltage range.

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Variants Currently In Production

Table 11: Differences between variants of Module TE0741.

Technical Specifications

Absolute Maximum Ratings

Table 12: Absolute maximum ratings ratings.

Recommended Operation Conditions

Table 13: Recommended operation conditions.

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• Module size: 50 mm × 40 mm
• Mating height with standard connectors: 8mm
• PCB thiknessthickness: 1.6mm

All dimensions are shown in mm.

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Figure 7: Physical Dimensions of the TE0741-02 board.

Operating Temperature Ranges

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The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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