TE0741 TRM

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Overview

The Trenz Electronic TE0741 is a FPGA module integrating an AMD Kintex 7 FPGA with two Quad GTP transceivers, Quad SPI Flash memory for configuration and operation and a Programmable Clock Generator. Numerous configurable I/O' are provided via high-speed connections.

Refer to http://trenz.org/te0741-info for current online available documentation.

Key Features

FPGA
- AMD Kintex 7 FPGA ¹⁾: XC7K70T / XC7K160T / XC7K325T / XC7K410T
- Speed grade ¹⁾: -1 / -2 / -3 / -1L / -2 L
- Temperature Range ²⁾: C / E / I
- Package: FBG676
Storage
- SPI Flash 32 MB (with XiP support) ²⁾
On Board
- System Controller
- Programmable Clock Generator for FPGA PL and MGTs
- LEDs:
  - 2x user (red and green)
  - 2x status (both green)
Interface
- Trenz 4 x 5 SoM 3x B2B Connector (Samtec LSHM) socket:
  - GTYP: 8x MGT and 2x CLK
  - FPGA variant XC7K70T:
    - IO HR: 110x SE / 51x DIFF
  - FPGA variants XC7K160T / XC7K325T / XC7K410T:
    - IO HR: 160x SE / 75x DIFF
Power
- Single or dual power supply operation
- System management and power sequencing
- Monitoring for main Voltage Rails
Dimension
- 40 mm x 50 mm
Notes

¹⁾ Available as assembly variant or upon request.
²⁾ Other sizes/devices, which are pin/package-compatible, upon request.

Block Diagram

TE0741 block diagram

Main Components

TE0741 main components

AMD Kintex 7 FPGA, U1
QSPI Flash, U4
Clock Generator, U2
Oscillator for Clock Generator, U3
System Controller, U7
Supply Monitor, U11
LEDs user, D1 - green, D2 - red
LEDs status, D3 - Done, D4 - System Controller
B2B connectors, JM1, JM2, JM3

Initial Delivery State

Storage device name	Content	Notes
Quad SPI Flash, U4	Not programmed
System Controller, U7	Firmware	Refer to TE0741 CPLD Firmware / TE0741 CPLD for more information.
Programmable Clock Generator, U2	Not programmed

Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector Type	Designator	Interface	IO count	Notes
B2B	JM1	MGT	3x MGT (RX/TX)	FPGA bank 115
B2B	JM3	MGT	1x MGT (RX/TX)	FPGA bank 115
B2B	JM3	MGT	4x MGT (RX/TX)	FPGA bank 116
B2B	JM3	MGT CLK	1x DIFF	FPGA bank 115
B2B	JM3	MGT CLK	1x DIFF	FPGA bank 116
B2B	JM1	IO HR	48x SE / 24x DIFF	FPGA bank 13
B2B	JM1	IO HR	8x SE	FPGA bank 14
B2B	JM3	IO HR	4x SE / 2x DIFF	FPGA bank 14
B2B	JM3	IO HR	8x SE / 16x DIFF	FPGA bank 16
B2B	JM2	IO HR	18x SE / 9x DIFF	FPGA bank 15
B2B	JM2	IO HR	48x SE / 24x DIFF	FPGA bank 12
B2B	JM2	IO HR	2x SE	FPGA bank 12

Board Connectors

Test Points

Test Point	Bottom	Signal
TP1	x	VIN
TP2	x	3.3V
TP3	x	VCCIO16
TP4	x	VCCIO15
TP5	x	VCCIO12
TP6	x	VCCIO13
TP7	x	1V
TP8	x	1V_MGT
TP9	x	1.2V_MGT
TP10	x	1.8V
TP11	x	GND
TP12	x	GND

Test Points Information

On-board Peripherals

Chip/Interface	Designator	Connected to	Notes
AMD Kintex 7 FPGA	U1	QSPI Flash, U4 Clock Generator, U2 LEDs B2B, JM1, JM2, JM3
QSPI Flash	U4	FPGA, U1
Clock generator	U2	Oscillator, U3 FPGA, U1
System Controller	U7	FPGA, U1 LED Status, DCDCs B2B, JM1, JM2	Refer to TE0741 CPLD Firmware / TE0741 CPLD for further information.
Oscillator	U3	Clock Generator, U2

On board peripherals

Configuration and System Control Signals

Signal Name	Connector.Pin	Direction ¹⁾	Description
EN1	JM1.28	IN	SoM power enable.
PGOOD	JM1.30	OUT	SoM voltage rail status. Low, if power failed, internal pull-up activated. ²⁾
MODE	JM1.32	IN	Currently not used. ²⁾
JTAGMODE	JM1.89	IN	Select JTAG target, high for System Controller and low for FPGA. ²⁾
JTAG (TMS / TDI / TDO / TCK)	JM2.93 / JM2.95 / JM2.97 / JM2.99	Signal dependent
RESIN	JM2.18	IN	SoM reset signal. ²⁾

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
- INOUT: Bidirectional signal.
- Signal dependent: A Signal can have different functions and directions as part of a bus.

²⁾ Firmware dependent. Refer to TE0741 CPLD Firmware / TE0741 CPLD for further information.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name / Schematic Name	Connector.Pin	Direction ¹⁾	Notes
VIN	JM1.1 / JM1.3 / JM1.5 JM2.2 / JM2.4 / JM2.6 / JM2.8	IN	Main supply.
3.3VIN	JM1.13 / JM1.15	IN	Management supply.
VCCIO12	JM2.7 / JM2.9	IN	FPGA IO bank supply.
VCCIO13	JM1.9 / JM1.11	IN	FPGA IO bank supply.
VCCIO15	JM2.5	IN	FPGA IO bank supply.
B15_VREF	JM2.29	IN	FPGA IO bank reference voltage.
VCCIO16	JM2.1 / JM2.3	IN	FPGA IO bank supply.
B16_VREF	JM3.56	IN	FPGA IO bank reference voltage.
VBAT_IN	JM1.79	IN	FPGA back up supply.
3.3V	JM2.10 / JM2.12 / JM2.91	OUT	External IO supply.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Module power rails.

Recommended Power up Sequencing

A good starting point into your own custom carrier board design can be the familiarisation with Trenz Electronic's Carrier designs for the this SoM. The Trenz 4 x 5 SoM Integration Guide and our FAQ - PCB Design hold valuable information.

See also AMD data sheet Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) for additional information.

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration SoM signal setup.	See Configuration and System Control Signals.
1	VIN 3.3VIN	3.3 V - 5.5V (±5%) 3.3 V (±3 %)	-	Main supply. Management supply.
2	EN1	3.3 V (± 5 %) ²⁾	PU ¹⁾, 3.3 V	SoM power enable.
3	PGOOD	3.3 V	- ^{1), 2)}	Signals to carrier all voltage rails are active.
4	VCCIO12 VCCIO13 VCCIO15 VCCIO16	1.2 V - 3.3 V (±3 %) 1.2 V - 3.3 V (±3 %) 1.2 V - 3.3 V (±3 %) 1.2 V - 3.3 V (±3 %)	- - - -	When PGOOD is high (3.3V), enable SoC IO bank supplies.

¹⁾ (on module)

²⁾ Firmware dependent. Refer to TE0741 CPLD Firmware / TE0741 CPLD for further information.

Refer to Trenz 4 x 5 SoM Integration Guide, FAQ - PCB Design and AMD data sheet Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) for more information.

Baseboard Design Hints

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)

Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order number	Connector on baseboard	compatible to	Mating height
23836	REF-189016-01	LSHM-150-02.5-L-DV-A-S-K-TR	6.5 mm
	LSHM-150-03.0-L-DV-A-S-K-TR	LSHM-150-03.0-L-DV-A-S-K-TR	7.0 mm
23838	REF-189016-02	LSHM-150-04.0-L-DV-A-S-K-TR	8.0 mm
	LSHM-150-06.0-L-DV-A-S-K-TR	LSHM-150-06.0-L-DV-A-S-K-TR	10.0mm
26125	REF-189017-01	LSHM-130-02.5-L-DV-A-S-K-TR	6.5 mm
	LSHM-130-03.0-L-DV-A-S-K-TR	LSHM-130-03.0-L-DV-A-S-K-TR	7.0 mm
24903	REF-189017-02	LSHM-130-04.0-L-DV-A-S-K-TR	8.0 mm
	LSHM-130-06.0-L-DV-A-S-K-TR	LSHM-130-06.0-L-DV-A-S-K-TR	10.0mm

Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking height	Speed rating
12 mm, Single-Ended	7.5 GHz / 15 Gbps
12 mm, Differential	6.5 GHz / 13 Gbps
5 mm, Single-Ended	11.5 GHz / 23 Gbps
5 mm, Differential	7.0 GHz / 14 Gbps

Speed rating.

Current Rating

Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings

Shock: 100G, 6 ms Sine
Vibration: 7.5G random, 2 hours per axis, 3 axes total

Manufacturer Documentation

	File	Modified
	PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File lshm_dv.pdf LSHM catalog page	Apr 07, 2016 by Thorsten Trenz
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	PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File REF-189016-01.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File REF-189016-02.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File REF-189017-01.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File REF-189017-02.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report	Apr 07, 2016 by Thorsten Trenz
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	PDF File tc0929--2611_qua(1).pdf Shock and vibration report	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View

Technical Specifications

Absolute Maximum Ratings ^*)

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
VIN	SoM main supply.	-0.3	7	V
3.3VIN	SoM management supply.	-0.3	3.6	V
VCCIO12	FPGA IO bank supply.	–0.5	3.6	V
VCCIO13	FPGA IO bank supply.	–0.5	3.6	V
VCCIO15	FPGA IO bank supply.	–0.5	3.6	V
VCCIO16	FPGA IO bank supply.	–0.5	3.6	V
VBAT_IN	Memory backup supply.	–0.5	2.0	V

Absolute maximum ratings

^*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
Cooling solution, active and or passive cooling.
Climate or environmental conditions besides ambient temperature range.
Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be locked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

Parameter	Min	Max	Unit	Reference Document
VIN	3.135	5.775	V	Refer to schematic.
3.3VIN	3.201	3.399	V	Refer to schematic.
VCCIO12	1.164	3.399	V	Refer to DS182 datasheet.
VCCIO13	1.164	3.399	V	Refer to DS182 datasheet.
VCCIO15	1.164	3.399	V	Refer to DS182 datasheet.
VCCIO16	1.164	3.399	V	Refer to DS182 datasheet.
VBAT_IN	1.067	1.854	V	Refer to DS182 datasheet.

Recommended operating conditions.

Physical Dimensions

Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 ±10 % mm.

All dimensions are shown in millimeters.

Physical Dimension

Currently Offered Variants

Trenz shop TE0741 overview page*
English page	German page

*) Module article name encoding table: 7 Series Spartan, Artix and Kintex modules

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

The hardware revision number is located on the PCB next to the module identifier, separated by a dash.

Board hardware revision number.

Date	Revision	Changes	Documentation Link
2023-05	REV05	Added Pull-up R34 for net EN1. Added Pull-upR43 for net PROG B. Changed component Q1 (TPS2708 EADDCR) to U17(MP5077GG-Z). Added external compensation for U14-U15 (2 LTM4638 in parallel mode). Added diode between nets INIT and PROG B. Removed power supervisor TPS3805H33DCKR. Added power sense monitor U11 STM6710LWB6F. Updated Overview. Updated Power diagram. Some nets from banks 32, 33, 34 were connected to GND for increased ESD protection. Added Pull-upresistor R49 for net CLK EN on page 18. Changed ID nets state on page 9 from '100' (rev4) to '101' (rev5). Added UKCA Logo.	REV05 PCN
2021-11	REV04	Replaced all DCDC (reason: not recommended use Enpirion DCDC). Remove Traceability Pad (reason: EOL). Added additional resistor for VBAT (reason: possibility using external VBAT from Carrier Board). Full updated LIB components. Optimisation PCB routing.	REV04 PCN
2017-10	REV03	Fixed connection DCDC for parallel operations. Update Razorbeam Connectors, full update lib. Added serial number (traceability pad). Changed ferrite beads L1..L4 size 0402 on BKP0603HS121-T. Added thermal vias to mounting holes.	REV03 PCN
2014-06	REV02		REV02
2013-11	REV01	Initial release	REV01

Hardware Revision History

Document Change History

Date	Revision	Contributors	Description
2026-02-19	v.72	Kilian Jahn	Updated to TRM Template 4.3.2
2020-03-06	v.65	John Hartfiel	Update LED description
2018-08-29	v.64	John Hartfiel	Update CPLD description and links
2017-11-10	v.63	John Hartfiel	Replace B2B connector section
2017-08-28	v.60	Jan Kumann	New power-on diagram. Few improvements. Template revision added.
2017-07-20	v.57	John Hartfiel	Correction: PLL default output CLKs.
2017-06-07	v.55	Jan Kumann	Minor formatting
2017-06-02	v.50	Jan Kumann	REV03 specific update.
2017-01-22	v.42	Jan Kumann	New block diagram added.
2017-01-13	v.38	Jan Kumann	New product images and physical dimension drawings. Formatting improvements and small corrections.
2017-01-12	v.21	John Hartfiel	Correction: B2B and FPGA bank location.
2016-12-14	v.19	Ali Naseri	TRM revision.
2013-12-02	v.1	Antti Lukats, Jon Bean	Initial version.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

2025-08-01

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