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- 6-pin header J26 for selecting Bank34 VCCIO voltage
- 6-pin header J27 for selecting XMOD/JTAG reference voltage
- Samtec Razor Beam™ LSHM-150 B2B connector JM1
- Samtec Razor Beam™ LSHM-150 B2B connector JM2
- JTAG/UART header JX1 ('XMOD FTDI JTAG Adapter' compatible pin-assignment)
- Ultra small SMT coaxial connector J5
- Ultra small SMT coaxial connector J6
- Ultra small SMT coaxial connector J7
- Ultra small SMT coaxial connector J8
- User LED D1 (green)
- User LED D2 (red)
- LED D3 (red) indicating 'Programming DONE'-signal from module's FPGA
- SFP+ Connector J1
- 10-pin header soldering-pads J4 for access to SoM's IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, 3.3V_OUT from module)
- 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter' compatible pin-assignment) with 2 4 additional pins for reference-clock input to 4 x 5 cm SoM and differential pair for ADC
- 50-pin header soldering-pads J20 for access to SoM's IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, Bank34 VCCIO voltage)
- 50-pin header soldering-pads J17 for access to SoM's IO-banks (LVDS-pairs possible, VCCIO voltages: 3.3V, V_CFG from module)
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The RX-/TX-data-lanes are connected to B2B-connector JM1, the control-lines are connected to pins on B2B-connector JB1 and are MIO-pins in standard TE module's pin-assignmentJM2.
On this SFP+ connector, on both 4 x 5 SoMs TE0741 and TE0841 MGT-lane 3 2 is accessible at mounted 4 x 5 SoM TE0714.
The pin-assignment of the SFP connector is in detail as fellows:
| SFP+ pin | SFP+ pin netname | B2B | Note | |
|---|---|---|---|---|
| Transmit Data + (pin 18) | MGT_TX3TX2_P | JB2JM1-2614 | - | |
| Transmit Data - (pin 19) | MGT_TX3TX2_N | JB2JM1-2816 | - | |
| Receive Data + (pin 13) | MGT_RX3RX2_P | JB2JM1-257 | - | |
| Receive Data - (pin 12) | MGT_RX3RX2_N | JB2JM1-279 | - | |
| Receive Transmit Fault (pin 2) | MIO10 | SFP0_TX_FAULT | JM2-42JB1-96 | - |
| Receive Transmit disable (pin 3) | not connected | SFP0_TX_DIS | JM2-44- | - |
| MOD-DEF2 (pin 4) | MIO13SFP0_SDA | JB1JM2-9846 | 3.3V pull-up, (usable as I²C-SDA) | |
| MOD-DEF1 (pin 5) | MIO12SFP0_SCL | JB1JM2-10048 | 3.3V pull-up, (usable as I²C-SCL) | |
| MOD-DEF0 (pin 6) | MIO11SFP0_M0DEF0 | JB1JM2-9440 | - | |
| RS0 (pin 7) | not connectedSFP0_RS0 | JM2-38 | - | |
| LOS (pin 8) | MIO0SFP0_LOS | JB1JM2-8834 | - | |
| RS1 (pin 9) | not connectedSFP0_RS1 | JM2-32 | - |
Table 1: SFP+ connector pin-assignment
Bridged MGT-Lanes on B2B Connector JB1 and JB2
The TEBA0841 Carrier Board is mainly for the use the SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, the 5 RX/TX differential pairs are bridged and looped backed on-board, hence the transmitted data on this MGT-lanes are received simultaneously by the same MGT-lane.
The MGT-lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted:
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JB2-8 (MGT_TX0_N)
JB2-10 (MGT_TX0_P)
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JB2-7 (MGT_RX0_N)
JB2-9 (MGT_RX0_P)
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JB2-7 to JB2-8
JB2-9 to JB2-10
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JB2-14 (MGT_TX1_N)
JB2-16 (MGT_TX1_P)
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JB2-13 (MGT_RX1_N)
JB2-15 (MGT_RX1_P)
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JB2-13 to JB2-14
JB2-15 to JB2-16
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JB2-20 (MGT_TX2_N)
JB2-22 (MGT_TX2_P)
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JB2-19 (MGT_RX2_N)
JB2-21 (MGT_RX2_P)
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JB2-19 to JB2-20
JB2-21 to JB2-22
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JB1-3 (MGT_TX7_P)
JB1-5 (MGT_TX7_N)
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JB1-9 (MGT_RX7_P)
JB1-11 (MGT_RX7_N)
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JB1-3 to JB1-9
JB1-5 to JB1-11
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JB1-15 (MGT_TX6_P)
JB1-17 (MGT_TX6_N)
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JB1-21 (MGT_RX6_P)
JB1-23 (MGT_RX6_N)
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JB1-15 to JB1-21
JB1-17 to JB1-23
JTAG/UART Interface
The
Table 2: Bridging-table of the MGT-lanes for mounted 4 x 5 SoM TE0741.
| Note |
|---|
| Note: The MGT-lanes of the 4 x 5 SoM TE0841 have different designations. See Schematic of the particular module. |
USB Interface
The TEBA0841 carrier board has one physical USB-connector J10, which is available as Micro-USB port. The USB interface J10 can be operated in Device- and OTG-modes. The Micro-USB port-pins are routed to the USB-OTG-interface on B2B-connector JB2. There are usually corresponding USB-PHYs on SoMs supported by the Carrier Board TEBA0841.
JTAG Interface
The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment.:
| JX1 pin | JX1 pin net-name | B2B |
|---|---|---|
| C (pin 4) | TCK | JB3JM1-10090 |
| D (pin 8) | TDO | JB3JM1-9888 |
| F (pin 10) | TDI | JB3JM1-9686 |
| H (pin 12) | TMS | JB3JM1-9492 |
| A (pin 3) | MIO15B14_L25 | JB1JM2-8697 |
| B (pin 7) | MIO14B14_L0 | JB1JM2-9199 |
| E (pin 9) | BOOTMODE | JB1-90 (JTAGSELECT)JM2-100 |
| G (pin 11) | RESINPROG_B | JB3JM2-1794 |
Table 3: JTAG header JX1 pin-assignment
There is also the option to mount and solder a 2-row 16-pin header to the place-holder J3, which has the same pin-assignment as header JX1, but with also two additional two pins (15,16) as LVDS-pair , to put to supply the mounted 4 x 5 SoM with an external reference clock-signal to the mounted 4 x 5 SoM. The clock-signal is put linked to to the SoM via B2B-connector pins JB2-32 (MGT_CLK0_N) and JB2-34 (MGT_CLK0_P).
Further two additional pins (13, 14) are designated as LVDS-pair for analog signals and routed to the ADC-unit of the SoM. This LVDS-pair is fused with 1K serial resistors on both conductors and has on the B2B-connector JM1 the pins JM-25 and JM-27 with the net-names 'ADC_P' and 'ADC_N'.
On both interfaces (JX1, J3), the pins with the net-names MIO14 and MIO15 B14_L25 and B14_L0 are available as user IO's which could be used as UART-interface for example.
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