Page History
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| CLK Output | FPGA Bank | FPGA Pin | IO Standard | Net Name | Default Frequency | Note | |
|---|---|---|---|---|---|---|---|
| CLK0 | 34 | K4/J4 | DIFF_SSTL15 | CLK0_P/N | -- | only on PCB REV02 | |
| CLK1ACLK1 | - | - | CLK50M | 50 MHz | PHY chip RMII reference clock. | ||
| CLK1CLK1B | 34 | R4 | CLK50M2 | 50 MHz | -- | only on PCB REV02 | |
| CLK2 | 216 | F6/E6 | Auto | MGT_CLK0_P/N | 125 MHz | GTP transceiver clock. | |
| CLK3 | 35 | H4/G4 | DIFF_SSTL15 | PLL_CLK_P/N | 50 MHz |
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-03-01 | John Hartfiel | Update Clocking Section | |
| 2017-01-26 | V3 | Jan Kumann | New block diagram. Few corrections. |
| 2017-01-20 | V2
| Jan Kumann | Revised version. |
| 2013-12-02 | V0.1 | Antti Lukats | Work in progress. |
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