Page History
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teCORE™ IP Facts Table | |
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Supported Device Family | Zynq® -7000, 7 Series, UlttraScaleUltraScale, UltraScale+ |
Supported User Interfaces | AXI4-Stream |
Resources | EFUSE_USR |
Provided with Core | |
Documentation | Product Guide |
Design Files | VHDL Source Code |
Tested Design Flows | |
Design Entry | Vivado® Design Suite, IP Integrator |
Simulation | Vivado Simulator |
Synthesis | Vivado Synthesis |
Support | |
Provided by Trenz Electronic GmbH |
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