Page History
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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properlylow when EN1 is low or module power is invalid. |
| JTAGEN | Input | JTAG select | Low for normal operation, high for System Controller CPLD access. |
| EN1 | Input | Power Enable | When forced low, pulls POR_B low to emulate power on reset. |
| NOSEQ | - | No function | Not used. |
| MODE | - | No function | Not used. |
Pin usages depends on CPLD Firmware, see: TE0712 CPLD
LEDs
The TE0712 module has 2 LEDs which are connected to the System Controller CPLD. Once FPGA configuration has completed these can be used by the user's design.
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-03-01 | John Hartfiel | BUGFIX in the description of System Controller IO section | |
| 2017-03-01 | v3.1 | John Hartfiel | Update Clocking Section |
| 2017-01-26 | V3 | Jan Kumann | New block diagram. Few corrections. |
| 2017-01-20 | V2
| Jan Kumann | Revised version. |
| 2013-12-02 | V0.1 | Antti Lukats | Work in progress. |
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Overview
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