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Refer to https://shopwiki.trenz-electronic.de/de/Download/?path=Trenz_Electronicdisplay/PD/TE0714+TRM for the downloadableonline version of this manual and the rest of available documentation. |
The Trenz Electronic TE0714 is an industrial-grade SoM (System on Module) based on Xilinx Artix-7, 16 MByte Flash memory and powerful switching mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
Block Diagram
Main Components
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Key Features
Xilinx Artix-7 FPGA (A15T, A35T, A50T)
- Rugged for
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- shock and
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- high vibration
- 16 MByte QSPI Flash
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- memory
- Differential MEMS
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- oscillator for
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- MGT clocking
- MEMS
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- oscillator for PL
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- clocks (Optional)
- Plug-
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- on module with 2 × 100-
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- pin high-speed hermaphroditic strips
- 144 FPGA I/O's (Max 68
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- differential)
- XADC
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- analog input
- 4 GTP (
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- high-
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- performance transceiver)
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- lanes
- GT
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- reference clock inputs
- Optimized I/O and
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- power pins for good signal integrity
- On-board
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- high-
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- efficiency DC-DC
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- converters
- Power
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- supply for
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- all on-board components
- eFUSE
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- bit-
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- stream encryption (AES)
- One
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- user configurable LED
Different configurations for cost and performance optimization available upon request. Available options are:
- FPGA Type (A15T, A35T, A50T), temperature grade
- GT
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- clock frequency (or none if not implemented)
- PL
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- clock frequency and precision (or none if not implemented)
- Config and B14
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- bank Voltage: 1.8V or 3.3V
- SPI Flash type (or none if not implemented)
- LED Color (or none if not implemented)
- PUDC Pin strapping (pull high or pull down)
- GT
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- power enable pin strapping (default power enabled or disabled)
Block Diagram
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Main Components
- Xilinx Artix-7 FPGA (XC7A series), U4
- 16 MByte SPI Flash, U7
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 25 MHz oscillator, U8
- Single output low-dropout linear regulator (1.2V_MGT), U6
- Single output low-dropout linear regulator (1.0V_MGT), U5
- Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
- Red indication LED, D4
- Step-down DC-DC converter (1.0V), U1
- PFET load switch with configurable slew rate (3.3V), Q1
- Low-power step-down DC-DC converter (1.8V), U3
- Voltage detector for circuit initialization and timing supervision, U23
Initial Delivery State
Storage device name | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
eFUSE USER | Not programmed | |
eFUSE Security | Not programmed |
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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14 | JM1 | 6 | VCCIO_0 | |
14 | JM2 | 36 | VCCIO_0 | NB! 17 LVDS pairs possible. |
15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. |
34 | JM1 | 48 | VCCIO34 | Supplied by the baseboard. |
216 | JM1 | 16 | MGT_AVCC MGT_AVTT | 4 x GTP lanes. |
Please refer to the Pin-out tables page for additional information.
JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA device is provided through connector JM1.
Signal Name | B2B Pin |
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TCK | JM1:89 |
TDI | JM1:85 |
TDO | JM1:87 |
TMS | JM1:91 |
On-board LED's
There is one LED on TE0714 module:
LED | Color | FPGA | Notes |
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D4 | Red | K18 |
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Clocking
Clock | Default Frequency | IC | FPGA | Notes |
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CLK125MHz | 25 MHz | U8 | T14 | Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V IO-Standard on I/O standard of the FPGA bank. |
MGT_CLK | 125MHz | U2 | B6/B5 | Frequency depends on the module variant |
Boot
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Process
Boot mode is controlled by the MODE signal on the board to board (B2B) connector:
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Note |
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SPI D2 and D3 have no pull-ups on the module so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register. |
LED's
There is one LED on TE0714 module:
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LED
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Color
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FPGA
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Notes
On-board Peripherals
16 MByte Quad SPI Flash
On-board SPI flash memory S25FL127S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash. By default this bit is set to high at the manufacturing plant. |
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D4
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Red
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K18
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Power and Power-On Sequence
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Variants Currently In Production
Module Variant | FPGA Chip Model |
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B14/Config Voltage [V] | R27 (VCCIO_0 on JM2 Pin 54) | SPI Flash |
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LED
D4TE0714-02-35-2I |
XC7A35T-2CSG325I | 3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S |
TE0714-02-35-2IC6 |
XC7A35T-2CSG325I | 1.8 | JM2 Pin 54 = Open | N25Q128 |
TE0714-02- |
50-2I |
XC7A50T- |
2CSG325I |
3.3 | JM2 Pin 54 = VCCIO_0 (3.3 V) | S25FL127S |
TE0714-02-50-2IC6 |
XC7A50T-2CSG325I | 1.8 | JM2 Pin 54 = Open | N25Q128 |
Note |
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On REV 01 JM2 Pin 54 was connected to GND. When R27 is not populated, REV 02 is backwards compatible to REV 01. When R27 is set, check your baseboard to not connect this pin to GND. For all new baseboards JM2.54 should be used as VCCIO output (it will then be 1.8V or 3.3V depending the voltage settings on the module. |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
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VIN supply voltage | -0.1 |
6. |
0 | V |
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HR I/O |
banks supply voltage (VCCO) | -0.5 | 3.6 | V |
Xilinx datasheet DS181 |
HR I/O banks input voltage |
-0.4 | VCCO |
+ 0.55 | V |
Xilinx datasheet DS181 |
GTP transceivers Tx/Rx input voltage | -0.5 | 1.26 | V |
Xilinx datasheet DS181 | |||
Voltage on module JTAG pins | -0.4 | VCCO_0 + 0.55 | V |
Xilinx datasheet DS181 | |||
Storage temperature | -40 | +85 | °C |
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Recommended Operating Conditions
Parameter | Min | Max | Units | Notes |
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VIN supply voltage | 3.135 | 3.45 | V |
- | |||
HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V |
Xilinx datasheet DS181 |
HR I/O banks input voltage |
-0.20 | VCCO + 0.20 | V |
Xilinx datasheet DS181 | |||
Voltage on module JTAG pins | 3.135 | 3.465 | V |
3.3V CONFIG Bank option
Xilinx datasheet DS181 |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Note |
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Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7. |
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Physical Dimensions
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm. Additional sketches, drawings and schematics can be found here.
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Operating Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0 °C to +70 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40 °C to +85 °C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
Variant | Weight in g | Note |
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2IC6 | 8.3 | Plain Module |
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Date | Revision | Authors | Description |
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2017-05-28 | Jan Kumann | Board-to-Board I/O section added. New physical dimensions images. Documents sections rearranged. | |
2017-03-20 | V.26 | John Hartfiel | Notes on Clocking section. |
2017-01-27 | v.25 | Jan Kumann | New block diagram. |
2016-12-01 | v.17 | Jan Kumann | Changes in the document structure, few corrections. |
2016-11-18 | v.14 | Thorsten Trenz, Emmanuel Vassilakis | Hardware revision 02 specific changes. |
2016-06-01 | v.9 | Antti Lukats | Initial version. |
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Include Page | ||||
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Refer to https://wiki.trenz-electronic.de/display/PD/TE0713+TRM for online version of this manual and the rest of available documentation.