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Micro SD memory card connector J9 with detect switch is connected to the Zynq Soc PS MIO bank 500. See also section Default MIO Mapping.

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FPGA IO Banks Pin Mapping

BankZynq PinNameConnected To
34G14PUDCJumper J14
35G15DSI_XASystem Controller CPLD, pin 16
35F15DSI_XBSystem Controller CPLD, pin 17

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GPIO to Header J8 Interface Mapping

GPIO NameZynq PinJ8 Pin GPIO NameZynq PinJ8 Pin
GPIO2K153 GPIO15N1310
GPIO3J145 GPIO16L1336
GPIO4H127 GPIO17G1111
GPIO5N1429 GPIO18H1112
GPIO6R1531 GPIO19R1235
GPIO7L1426 GPIO20M1438
GPIO8L1524 GPIO21P1540
GPIO9J1321 GPIO22H1315
GPIO19H1419 GPIO23J1116
GPIO11J1523 GPIO24K1118
GPIO12M1532 GPIO25K1322
GPIO13R1333 GPIO26L1237
GPIO14M128 GPIO27G1213

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Default MIO Mapping

Bank 500 MIOs

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