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Default MIO Mapping
Bank 500 MIOs
MIO | Function | Notes |
---|---|---|
0 | MIO0_INT | Interrupt signal from I2C MUX. |
1 | SPI0_CS | SPI chip select. |
2 | SPI0_DQ0/M0 | Bi-directional data line 0 |
3 | SPI0_DQ1/M1 | Bi-directional data line 1 |
4 | SPI0_DQ2/M2 | Bi-directional data line 2 |
5 | SPI0_DQ3/M3 | Bi-directional data line 3 |
6 | SPI0_SCK | SPI clock. |
7 | MIO7 | RESETB of USB3320 chip, U18 |
8 | MIO8 | System Controller CPLD pin 28 |
9 | MIO9 | System Controller CPLD pin 29 |
10 | SD_D0 | Serial data 0. |
11 | SD_CMD | Command/Response. |
12 | SD_CLK | Serial clock. |
13 | SD_D1 | Serial data 1. |
14 | SD_D2 | Serial data 2. |
15 | SD_D3 | Serial data 3. |
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Bank 501 MIOs
MIO | Function | Notes |
---|---|---|
28 | OTG-DATA4 | ULPI bi-directional data bus. |
29 | OTG-DIR | Data bus direction control signal. |
30 | OTG-STP | Data throttle signal. |
31 | OTG-NXT | Data stream stop. |
32 | OTG-DATA0 | ULPI bi-directional data bus. |
33 | OTG-DATA1 | ULPI bi-directional data bus. |
34 | OTG-DATA2 | ULPI bi-directional data bus. |
35 | OTG-DATA3 | ULPI bi-directional data bus. |
36 | OTG-CLK | ULPI clock. |
37 | OTG-DATA5 | ULPI bi-directional data bus. |
38 | OTG-DATA6 | ULPI bi-directional data bus. |
39 | OTG-DATA7 | ULPI bi-directional data bus. |
48 | MUX_SCL | I2C clock to I2C MUX. |
49 | MUX_SDA | I2C data to/from I2C MUX. |
52 | MIO52 | System Controller CPLD pin 20 |
53 | MIO53 | System Controller CPLD pin 21 |
LED's
There are two LEDs on TE0726 module:
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