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The I/O signals are routed from the SoC's PL banks as LVDS-pairs to the B2B connectors.
Bank | Type | B2B Connector | I/O Signal Count | LVDS Pairs Count | VCCO Bank Voltage | Notes |
---|---|---|---|---|---|---|
12 | HR | J1 | 50 | 24 |
VCCIO_12 |
pins J1-54, J1-55 | supported voltages from 1.2V to 3.3V | |||
13 | HR | J1 | 50 | 24 |
VCCIO_13 |
pins J1-112, J1-113 | supported voltages from 1.2V to 3.3V | |||||
33 | HP | J3 | 50 | 24 | VCCIO_33 pins J3-115, J3-120 | supported voltages from 1.2V to 1.8V |
34 | HP | J2 | 50 | 24 |
VCCIO_34 |
pins J2-29, J2-30 | supported voltages from 1.2V to 1.8V | |||
35 | HP | J2 | 50 | 24 |
VCCIO_35 |
pins J2-87, J2-88 | supported voltages from 1.2V to 1.8V | |||||
500 | MIO | J2 | 5 | - | 1.8V | - |
501 | MIO | J3 | 12 | - | 1.8V | - |
Table 2: B2B connector pin-outs of available PL and PS banks of the SoC module
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The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:
Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs (LVDS pairs) |
---|---|---|---|---|---|
Bank 111 | GTX | J1 | 4 | MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21 MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15 MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9 MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5 | 1 reference clock signal (MGT_CLK3) from programmable 1 reference clock signal (MGT_CLK2) from B2B connector |
Bank 112 | GTX | J3 | 4 | MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70 MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64 MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58 MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52 | 1 reference clock signal (MGT_CLK1) from programmable 1 reference clock signal (MGT_CLK0) from B2B connector |
Table 3: B2B connector pin-outs of available MGT lanes of the SoC module
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JTAG Interface
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JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.
JTAG Signal | B2B Connector Pin |
---|---|
TCK | J1-143 |
TDI | J1-142 |
TDO | J1-145 |
TMS | J1-144 |
Table 4: B2B connector pin-out of JTAG interface
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System Controller I/O Pins
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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | B2B Connector Pin | Default Configuration | ||
---|---|---|---|---|---|---|
JTAG_EN | Input | JTAG Select | J1-148 |
At normal operation the JTAG-signals will be forwarded to the SoC module. VCCIO: PS_3.3V |
RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. |
PS_SRST | Input | Reset | J2-152 | Low-active system-reset pin of Zynq-chip. |
BOOTMODE | Input | Bootmode | J2-133 | Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133) the boot source of the Zynq-chip. See section "Boot Modes". |
PWR_PL_OK | Output | Power Good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. |
PWR_PS_OK | Output | Power Good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
Interface on B2B connectors
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