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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
Feature Summary
- Power Management
- Reset Management
- LED Control
Firmware Revision and supported PCB Revision
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| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| 200MHZCLK_EN | out | 30 | |
| BUTTON | in | 77 | Reset Button |
| CPLD_JTAG_TCK | 91 | not accessible as IO | |
| CPLD_JTAG_TDI | 94 | not accessible as IO | |
| CPLD_JTAG_TDO | 95 | not accessible as IO | |
| CPLD_JTAG_TMS | 90 | not accessible as IO | |
| DDR3_SCL | 43 | / currently_not_used | |
| DDR3_SDA | 42 | / currently_not_used | |
| DONE | in | 18 | FPGA Done |
| EN_1V8 | out | 58 | Power Enable |
| EN_3V3FMC | out | 60 | Power Enable |
| EN_FMC_VADJ | out | 51 | Power Enable |
| F1PWM | out | 98 | |
| F1SENSE | in | 99 | / currently_not_used |
| FEX_DIR | 19 | / currently_not_used | |
| FEX0 | 12 | / currently_not_used | |
| FEX1 | 15 | / currently_not_used | |
| FEX10 | 4 | / currently_not_used | |
| FEX11 | 10 | / currently_not_used | |
| FEX2 | 13 | / currently_not_used | |
| FEX3 | 9 | / currently_not_used | |
| FEX4 | 3 | / currently_not_used | |
| FEX5 | 7 | / currently_not_used | |
| FEX6 | 24 | / currently_not_used | |
| FEX7 | 17 | / currently_not_used | |
| FEX8 | 21 | / currently_not_used | |
| FEX9 | 25 | / currently_not_used | |
| FMC_PG_C2M | 69 | / currently_not_used | |
| FMC_PG_M2C | 68 | / currently_not_used | |
| FMC_PRSNT_M2C_L | 70 | / currently_not_used | |
| FMC_SCL | 49 | / currently_not_used | |
| FMC_SDA | 48 | / currently_not_used | |
| FMC_TCK | 27 | / currently_not_used | |
| FMC_TDI | 31 | / currently_not_used | |
| FMC_TDO | 32 | / currently_not_used | |
| FMC_TMS | 28 | / currently_not_used | |
| FMC_TRST | 36 | / currently_not_used | |
| FPGA_IIC_OE | 14 | / currently_not_used | |
| FPGA_IIC_SCL | 1 | / currently_not_used | |
| FPGA_IIC_SDA | 16 | / currently_not_used | |
| LED1 | out | 76 | Status LED D1 (green) |
| LTM_1V_IO0 | 86 | Power Good | |
| LTM_1V_IO1 | 88 | Power Good | |
| LTM_1V5_4V_IO0 | 85 | Power Good | |
| LTM_1V5_4V_IO1 | 83 | Power Good | |
| LTM_1V5_RUN | 74 | / currently_not_used | |
| LTM_4V_RUN | 75 | / currently_not_used | |
| LTM_SCL | 67 | / currently_not_used | |
| LTM_SDA | 66 | / currently_not_used | |
| LTM1_ALERT | 65 | / currently_not_used | |
| LTM2_ALERT | 64 | / currently_not_used | |
| PCIE_RSTB | out | 37 | PCIe Reset |
| PG_1V8 | in | 59 | Power Good |
| PG_3V3 | in | 61 | Power Good |
| PG_FMC_VADJ | in | 52 | Power Good |
| PLL_SCL | 2 | / currently_not_used | |
| PLL_SDA | 8 | / currently_not_used | |
| PROGRAM_B | out | 20 | FPGA PROG_B |
| VID0_FMC_VADJ | out | 53 | FMC EN5365QI power selection pin |
| VID1_FMC_VADJ | out | 54 | FMC EN5365QI power selection pin |
| VID2_FMC_VADJ | out | 57 | FMC EN5365QI power selection pin |
Functional Description
JTAG
CPLD JTAG is always enabled.
Power
Power sequence on will be executed over 4 States:
- State 1 IDLE: Wait until LTM_1V_IO0 (1V), LTM_1V_IO1 (1V) and LTM_1V5_4V_IO1 (4V) is available.
- State 2 PS1: Enables 1V8, 3V3FMC and VADJ. Wait until PG_1V8 (1.8V), PG_3V3 (3.3V) and PG_FMC_VADJ (FMC VADJ) is available.
- State 3 PS2: Wait until LTM_1V5_4V_IO0 (1.5V) is available
- State 4 RDY: All power on
Sstate machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to 1.8V.
Reset
PCIE_RSTB is low until power up sequencing is ready.
PROGRAM_B is controlled by push button after power up sequencing is ready.
CLK
200MHz CLK is enabled after power up.
Si55338 configuration is not implemented.
Button
Button is debounced and controls PROG_B signal from FPGA.
LED
LED is used as Status LED for power management and programming. Status depends on blink sequence.
| Status | Blink sequence | Comment |
|---|---|---|
| Error - Power IDLE state | ******** | ~5,8 Hz, |
| Error - Power PS1 state | *****ooo | ~0,7 Hz, duty cycle 5/8 |
| Error - Power PS2 state | ****oooo | ~0,7 Hz, duty cycle 4/8 |
| Power Ready, FPGA not programmed | ***ooooo | ~0,7 Hz, duty cycle 3/8 |
| -- | **oooooo | ~0,7 Hz, duty cycle 2/8, currently not used |
| -- | *ooooooo | ~0,7 Hz, duty cycle 1/8, currently not used |
| Power Ready, FPGa programmed | constant on |
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV01 |
| REV01 finishedWork in progress | ||||||||||||||||||||||
| 2017-05-29 | v.1 | --- |
| Initial release | |||||||||||||||||||||||
| All |
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Legal Notices
| Include Page | ||||
|---|---|---|---|---|
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