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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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LED is used as Status LED for power management and programming. Status depends on blink sequence.
| Status | Blink sequence | Comment |
|---|---|---|
| Error - Power IDLE state | ******** | ~5,8 Hz, |
| Error - Power PS1 state | *****ooo | ~0,7 Hz, duty cycle 5/8 |
| Error - Power PS2 state | ****oooo | ~0,7 Hz, duty cycle 4/8 |
| Power Ready, FPGA not programmed | ***ooooo | ~0,7 Hz, duty cycle 3/8 |
| -- | **oooooo | ~0,7 Hz, duty cycle 2/8, currently not used |
| -- | *ooooooo | ~0,7 Hz, duty cycle 1/8, currently not used |
| Power Ready, FPGa programmed | constant on |
Appx. A: Change History and Legal Notices
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To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||||
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| REV01 | REV01 |
| REV01 finished | ||||||||||||||||||||||||
| 2017-05-29 | v.1 | --- |
| Initial release | |||||||||||||||||||||||||
| All |
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Appx. A: Legal Notices
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