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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
Ethernet PHY connection
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pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).
Ethernet PHY to B2B connections
PHY Signal | B2B Connector Pin |
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SOUT_N | JM3-1 |
SOUT_P | JM3-3 |
SIN_N | JM3-2 |
SIN_P | JM3-4 |
PHY_MDI0_P | JM1-4 |
PHY_MDI0_N | JM1-6 |
PHY_MDI1_P | JM1-10 |
PHY_MDI1_N | JM1-12 |
PHY_MDI2_P | JM1-16 |
PHY_MDI2_N | JM1-18 |
PHY_MDI3_P | JM1-22 |
PHY_MDI3_N | JM1-24 |
USB Interface
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USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501. The I/O voltage is fixed at 1.8V and reference clock input of the PHY is supplied from the on-board 52.000000 MHz oscillator (U14).
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On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Clocking
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PS-CLK
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33.333333 MHz
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U6
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PS_CLK_500
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PS subsystem main clock.
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OTG-RCLK
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52.000000 MHz
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-
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USB3320C reference clock.
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Processing System (PS) Peripherals
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MIO16..27
MIO52..53
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width and clock frequency used.
Note |
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Clocking
Clock Signal | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS-CLK | 33.333333 MHz | U6 | PS_CLK_500 | PS subsystem main clock. |
OTG-RCLK | 52.000000 MHz | U14 | - | USB3320C reference clock. |
ETH-CLK | 25.000000 MHz | U9 | - | 88E1512 reference clock. |
Processing System (PS) Peripherals
Name | IC | ID | PS7 | MIO Bank | MIO | Notes |
---|---|---|---|---|---|---|
Gigabit Ethernet | 88E1512 | U8 | ETH0 | 501 | MIO16..27 MIO52..53 | MIO52 and MIO53 are also connected to the System Controller CPLD. |
USB OTG | USB3320C | U18 | USB0 | 501 | MIO28..39 | |
SPI Flash | S25FL256SAGBHI20 | U7 | QSPI0 | 500 | MIO1..6 | |
eMMC Flash | MTFC4GMVEA-4M IT1) | U15 | SD1 | 501 | MIO46..51 |
1) Different make and model may be installed on different module variants.
Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).
Ethernet PHY to FPGA/CPLD connections
PHY Signal | Zynq PS Signal | SC CPLD Pin | PHY Signal | Zynq PS Signal | SC CPLD Pin | |
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ETH-MDC | MIO52 | L14 | ETH-TXD2 | MIO19 | - | |
ETH-MDIO | MIO53 | K14 | ETH-TXD3 | MIO20 | - | |
PHY_LED0 | - | F14 | ETH-TXCTL | MIO21 | - | |
PHY_LED1 | - | D12 | ETH-RXCK | MIO22 | - | |
PHY_LED2 | - | C13 | ETH-RXD0 | MIO23 | - | |
PHY_CONFIG | - | C14 | ETH-RXD1 | MIO24 | - | |
ETH-RST | - | E14 | ETH-RXD2 | MIO25 | - | |
ETH-TXCK | MIO16 | - | ETH-RXD3 | MIO26 | - | |
ETH-TXD0 | MIO17 | - | ETH-RXCTL | MIO27 | - | |
ETH-TXD1 | MIO18 | - | CLK_125MHZ | - | G13 |
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RTC - Real Time Clock
Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
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A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD and contains globally unique 48-bit node address which is compatible with EUI-48TM specification. Upper 1/4 of the memory array contains 48-bit node address and is write protected.
On-board LEDs
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D2 | Green | LED1 | Controlled by System Controller CPLD firmware. |
D4 | Green | DONE | |
D5 | Red | LED2 | Controlled by System Controller CPLD firmware. |
Power and Power-On Sequence
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