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Overview




The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020 or XC7Z014S) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.

Key Features

  • Xilinx XC7Z SoC (XC7Z020 or XC7Z014S)
    • Processing system (PS):
      • XC7Z020: Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
      • XC7Z014S: Single-core ARM Cortex-A9 MPCore™ with CoreSight™
      • L1 cache: 32 KByte instruction, 32 KByte data per processor
      • L2 cache: Unified 512 KByte
    • Programmable logic (PL): Artix-7 FPGA
      • Programmable logic cells: 85K (XC7Z020), 65K (XC7Z014S)
      • Block RAM: 4.9 MByte (XC7Z020), 3.8 MByte (XC7Z014S)
      • DSP slices:  220 (XC7Z020), 170 (XC7Z014S)
      • Peak DSP performance: 276 GMACs (XC7Z020), 187 GMACs (XC7Z014S)
      • 2x 12 bit, MSPS ADCs with up to 17 differential inputs
  • 54 multiuse I/O (MIO) pins
  • 152 High-Range (HR) I/O pins (SelectIO interfaces)
  • System Controller CPLD (Lattice LCMXO2-1200HC)
  • Up to 1 GByte DDR3/L SDRAM memory (2 x 256 Mbit x 16, 32-bit wide data bus).
  • 32 MByte Quad SPI Flash memory
  • Gigabit Ethernet transceiver PHY (Marvell 88E1512)
  • MAC address serial EEPROM with EUI-48™ node identity (11AA02E48)
  • Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
  • 3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Optional!) 
  • Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
  • Atmel CryptoAuthentication element (Atmel ATSHA204A)
  • Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
  • User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
  • On-board high-efficiency DC-DC converters for all voltages used
  • Trenz 4 x 5 module socket connectors (3 x Samtec LSHM series connectors)
  • Evenly spread supply pins for good signal integrity
  • Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0720-03 block diagram.

Components and connections marked with dashed lines are optional or may be missing on some module variants, please contact us for additional information.

Main Components

 

Figure 2: Main components of the module.

  1. Xilinx Zynq XC7Z SoC, U5
  2. 4 Gbit DDR3/L SDRAM, U13
  3. 4 Gbit DDR3/L SDRAM, U12
  4. Low-power RTC with battery backed SRAM, U20
  5. 32 MByte Quad SPI Flash memory, U7
  6. Red LED (LED1), D5
  7. Green LED (LED2), D2
  8. System Controller CPLD, U19
  9. eMMC NAND Flash, U15
  10. 4A high-efficiency PowerSoC DC-DC step-down converter (1V), U1
  11. Green LED (DONE), D4
  12. B2B connector Samtec Razor Beam™ LSHM-130, JM3
  13. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  14. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  15. Hi-speed USB 2.0 ULPI transceiver, U18
  16. Gigabit Ethernet (GbE) transceiver, U8
  17. Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
  18. Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
  19. Low-dropout regulator (VBATT), U24
  20. DDR termination regulator, U4
  21. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
  22. Atmel CryptoAuthentication chip, U10
  23. 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
  24. Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
  25. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
  26. 3A PFET load switch with configurable slew rate (3.3V), Q1

Initial Delivery State

Storage device name

IC

Content

Notes

Quad SPI Flash

U7

Empty

-
eMMC NAND FlashU15Empty-
11AA02E48T EEPROMU17

Pre-programmed globally unique, 48-bit node address (MAC)

-
System Controller CPLDU19Standard firmware.Download firmware

Table 1: Initial state of programmable devices on delivery of the module.

Boot Process

By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

MODE Signal State

Boot Mode

High or open

QSPI

Low or connected to the ground

SD Card

Table 14: Boot modes.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

PL I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 152 HR GPIOs total.

BankTypeVoltageB2BI/O CountNotes
13HR GPIOVCCIO13JM24824 LVDS pairs
13HR GPIOVCCIO13JM22B13_IO0 and B13_IO25
33HR GPIOVCCIO33JM2189 LVDS pairs
34HR GPIOVCCIO34JM33618 LVDS pairs
35HR GPIOVCCIO35JM14824 LVDS pairs

Table 2: General PL I/O to B2B connectors information.


PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

MIOB2B PinBankVoltageNotes
0JM1-875003.3V
9JM1-915003.3V
10JM1-955003.3V
11JM1-935003.3V
12JM1-995003.3V
13JM1-975003.3V
14JM1-925003.3VAlso wired to U19-M4
15JM1-855003.3VAlso wired to U19-N4
40JM1-275011.8VZynq SoC SD0
41JM1-255011.8VZynq SoC SD0
42JM1-235011.8VZynq SoC SD0
43JM1-215011.8VZynq SoC SD0
44JM1-195011.8VZynq SoC SD0
45JM1-175011.8VZynq SoC SD0

Table 3: General PS MIO connections information.


For detailed information about the pin-out, please refer to the Pin-out tables. 

JTAG Interface

JTAG access to the Zynq SoC and System Controller CPLD is provided through B2B connector JM2.

JTAG Signal

B2B Connector Pin

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99

Table 4: JTAG pins connection.


JTAGMODE pin 89 in B2B connector JM1 is used to switch access between devices, low selects Zynq SoC, high selects System Controller CPLD.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
RESINInputReset inputActive low reset input, default mapping forces POR_B reset to Zynq PS.
PGOODOutputPower goodActive high when all on-module power supplies are working properly.
MODEInputBoot modeForce low for boot from the SD card. Latched at power-on only, not during soft reset!
EN1InputPower enableHigh enables the DC-DC converters and on-board supplies. Not used if NOSEQ is high.
NOSEQInputPower sequencingForces the 1.0V and 1.8V DC-DC converters always ON when high.
JTAGMODEInputJTAG selectKeep low for FPGA JTAG access.
MIO7Input/OutputGPIOConnected to System Controller CPLD pin P11, function depends on firmware

Table 5: System Controller CPLD special purpose pins description.

Quad SPI Interface

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.

MIOSignal NameU7 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table 6: Quad SPI interface MIOs and pins.

eMMC Interface

The TE0720 has on-board eMMC memory device (U15) except TE0720-03-1CR variant. At least three different eMMC devices have been used, please contact Trenz Electronic for more specific information.

MIOSignal NameU15 Pin
46MMC-D0H3
47MMC-CMDW5
48MMC-CLKW6
49MMC-D1H4
50MMC-D2H5
51MMC-D3J2

Table 7: eMMC interface MIOs and pins.

Ethernet Interface

The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see tables below.

SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).

Ethernet PHY to B2B connections

 PHY SignalB2B Pin
PHY SignalB2B Pin
SOUT_NJM3-1
PHY_MDI1_PJM1-10
SOUT_PJM3-3
PHY_MDI1_NJM1-12
SIN_NJM3-2
PHY_MDI2_PJM1-16
SIN_PJM3-4
PHY_MDI2_NJM1-18
PHY_MDI0_PJM1-4
PHY_MDI3_PJM1-22
PHY_MDI0_NJM1-6
PHY_MDI3_NJM1-24

Table 8: Ethernet PHY to B2B connections.


Ethernet PHY to Zynq SoC PS MIO ETH0 connections

PHY SignalSoC MIO
PHY SignalSoC MIO
ETH-TXCK16
ETH-RXCK22
ETH-TXD017
ETH-RXD023
ETH-TXD1

18


ETH-RXD124
ETH-TXD219
ETH-RXD225
ETH-TXD320
ETH-RXD326
ETH-TXCTL21
ETH-RXCTL27
ETH-MDC52
ETH-MDIO53

Table 9: Ethernet PHY to Zynq SoC connections.

USB Interface

Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq SoC PS USB0 via MIO28..39, bank 501.

USB PHY SignalWired toSoC MIO
OTG-DATA4U18-728
OTG-DIRU18-31

29

OTG-STPU18-2930
OTG-NXTU18-231
OTG-DATA0U18-332
OTG-DATA1U18-433
OTG-DATA2U18-534
OTG-DATA3U18-635
OTG-CLKU18-136
OTG-DATA5U18-937
OTG-DATA6U18-1038
OTG-DATA7U18-1339

Table 10: USB ULPI PHY to Zynq SoC connections.


USB PHY connection

USB PHY PinSC CPLD PinB2B NameNotes
REFSEL0..2--Reference clock frequency select, all set to GND = 52.000000 MHz.
RESETBB14, bank 1-Active low reset.
CLKOUT--ULPI output clock connected to Zynq PS MIO36.
DP, DM
OTG-D_P, OTG-D_NUSB data lines.
CPEN
VBUS_V_ENExternal USB power switch active high enable signal.
VBUS-USB-VBUSConnect to USB VBUS via a series of resistors, see reference schematic.
ID-OTG-IDFor A-device connect to the ground, for B-device leave floating.
SPK_LM5, bank 2-In USB audio mode a switch connects the DM pin to the SPK_L.
SPK_RM8, bank 2-In USB audio mode a switch connects the DP pin to the SPK_R.

Table 11: USB ULPI PHY connections.

I2C Interface

On-board I2C devices are connected to the System Controller CPLD which acts as a I2C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.

Signal NameSC CPLD PinSoC PinNotes
X1F1L16SCL, I2C clock.
X5J1P22SDA, I2C data out.
X7M1N22SDA, I2C data in.

Table 12: Zynq SoC to System Controller CPLD I2C bus.


I2C DeviceI2C AddressICNotes
ISL12020M RTC0x6FU20RTC registers.
ISL12020M SRAM0x57U20Battery backed RAM in RTC IC.
LSM303D0x1DU22Optional, not soldered on current production variants.

Table 13: I2C slave device addresses.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U19) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). The System Controller CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in System Controller CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Also interfaces like JTAG and I2C between the on-board peripherals and to the Zynq SoC are by-passed, forwarded and controlled.

Other tasks of the System Controller CPLD are monitoring of the power-on sequence and to indicate the programming state of the Zynq SoC FPGA.

For more detailed information, refer to the TE0720 System Controller CPLD firmware page.

DDR Memory

By default TE0720 module has two DDR3/L SDRAM chips arranged into 32-bit wide memory bus providing total on-board memory size up to 1 GBytes. Size of memory depends on the module variant, refer to the variants table.

Quad SPI Flash Memory

On-board 32-MByte QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

eMMC Flash Memory

eMMC Flash memory device(U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options). Depending on the module variant, different make and model of eMMC chips are available.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).


PHY SignalSC CPLD Pin
ETH-MDCL14
ETH-MDIOK14
PHY_LED0F14
PHY_LED1D12
PHY_LED2C13
PHY_CONFIGC14
ETH-RSTE14
CLK_125MHZG13

Table 15: Ethernet PHY to SC CPLD connections.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

RTC - Real Time Clock

Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

MAC-Address EEPROM

A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD pin M14 via single-I/O UNI/O serial interface and contains pre-programmed globally unique 48-bit node address compatible with EUI-48TM specification. Chip is programmed at the factory with a globally unique node address stored in the upper 1/4 of the memory array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use.

Atmel CryptoAuthentication Chip

The ATSHA204A Atmel CryptoAuthenticationTM chip (U10) is connected to the System Controller CPLD pin N14 via single-wire interface providing various security functions and features such as anti-counterfeiting, firmware/media protection, password validation, secure session key exchanging, secure data storage and more. Refer to the product datasheet for more information.

eCompass module

Optionally TE0720 module can be fitted with ultra-compact high-performance eCompass device (LSM303D, U22) featuring 3D accelerometer and 3D magnetometer.

Oscillators

SourceSignalFrequencyDestinationPin NameNotes
U6

PS-CLK

33.333333 MHz

U5

PS_CLK_500

Zynq SoC PS subsystem main clock.

U14

OTG-RCLK

52.000000 MHz

U18

REFCLK

USB3320C PHY reference clock.

U9ETH-CLK25.000000 MHzU8XTAL_IN88E1512 PHY reference clock.

Table 16: Oscillators.

On-board LEDs

LEDColorConnected toDescription and Notes
D2GreenLED1Controlled by System Controller CPLD firmware.
D4GreenDONE
D5RedLED2Controlled by System Controller CPLD firmware.

Table 17: On-board LEDs.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*
3.3VINTBD*

Table 18: Power Consumption.

 * TBD - To Be Determined.


Power Distribution Diagram

Figure 3: Power distribution diagram.

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).


Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use single 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

Use 3.3V or 1.8V output to enable external power supplies or power switches which are used to supply FPGA banks.

See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.

NOSEQ input signal

NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.


If NOSEQ input signal from the carrier board is low (logical 0), signals ON_1V0 and ON_1V8 can be driven by System Controller CPLD to control outputs of the U1 and U3 DC-DC converters.If NOSEQ input signal from the carrier board is high (logical 1), state of the ON_1V0 and ON_1V8 signals is irrelevant and DC-DC converters U1 and U3 outputs are always enabled.

Figure 4: Power sequencing.


Initial state of the ON_1V0 and ON_1V8 signals and therefore also functionality of the NOSEQ signal depend on the System Controller CPLD firmware.

Power Rails

B2B Name

B2B JM1 Pins

B2B JM2 Pins

Direction

Note
VIN1, 3, 52, 4, 6, 8InputSupply voltage from carrier board.
3.3VIN13, 15-InputSupply voltage from carrier board.
JTAG VREF-91Output

JTAG reference voltage.

Attention: Net name on schematic is "3.3VIN"

VCCIO359, 11-InputHigh range bank voltage from carrier board.
VCCIO33-5InputHigh range bank voltage from carrier board.
VCCIO13-7, 9InputHigh range bank voltage from carrier board.
VCCIO34-1, 3InputHigh range bank voltage from carrier board.
VBAT_IN79-InputRTC battery-buffer supply voltage.
3.3V-10, 12OutputInternal 3.3V voltage level.
1.8V39-OutputInternal 1.8V voltage level.
1.5V 1)-19OutputInternal 1.5V voltage level.

Table 19: Module power rails.

1) In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematic of the TE0720-03-L1IF for more information).

Bank Voltages

Bank          

Schematic Name

Voltage

Notes
5003.3V, VCCO_MIO0_5003.3V
5011.8V, VCCO_MIO1_5011.8V
5021.5V, VCCO_DDR_5021.5V
0 Config3.3V3.3V
13 HRVCCO131.2V to 3.3VSupplied by the carrier board.
33 HRVCCIO331.2V to 3.3VSupplied by the carrier board.
34 HRVCCIO341.25V to 3.3V

Supplied by the carrier board.
This FPGA Bank Power must be supplied and is not optional.
Minimum Voltage: B34 signals are used for CPLD/FPGA communication and  for PG generated by (TPS3805H33DCKR)

35 HRVCCIO351.2V to 3.3V

Supplied by the carrier board.

Table 20: Zynq SoC bank voltages.

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report 07 04, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report 07 04, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report 07 04, 2016 by Thorsten Trenz



Variants Currently in Production

Module VariantZynq SoC

RAM

eMMC

Size

Temperature

Range

B2B Connector

Height

TE0720-03-2IFXC7Z020-2CLG484I1 GByte4 GByteIndustrial4.0 mm
TE0720-03-2IFC3XC7Z020-2CLG484I1 GByte4 GByteIndustrial2.5 mm
TE0720-03-2IFC8XC7Z020-2CLG484I1 GByte32 GByteIndustrial4.0 mm
TE0720-03-L1IF XC7Z020-L1CLG484I512 MByte4 GByteIndustrial4.0 mm
TE0720-03-1CFXC7Z020-1CLG484C1 GByte4 GByteCommercial4.0 mm
TE0720-03-1CRXC7Z020-1CLG484C256 MByte-Commercial4.0 mm
TE0720-03-14S-1CXC7Z014S-1CLG484C1 GByte4 GByteCommercial4.0 mm
TE0720-03-1QFXA7Z020-1CLG484Q1 GByte4 GByteAutomotive4.0 mm

Table 21: Module variants currently in production.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.36.5

V

EP53F8QI datasheet.
3.3VIN supply voltage-0.13.75VTPS27082L and LCMXO2-1200HC datasheets.
Supply voltage for PS MIO banks-0.53.6VSee Xilinx DS187 datasheet.
I/O input voltage for MIO banks-0.4VCCO_MIO + 0.55V

See Xilinx DS187 datasheet.

(VCCO_MIO0_500, VCCO_MIO1_501)

Supply voltage for HR I/Os banks-0.53.6V

See Xilinx DS187 datasheet.

(VCCIO13, VCCIO33, VCCIO34, VCCIO35)

I/O input voltage for HR I/O banks-0.4VCCIO + 0.55VSee Xilinx DS187 datasheet.

Storage temperature

-40

+85

°C

-
Storage temperature without the ISL12020MIRZ, eMMC Flash and 88E1512 PHY installed-55+100°CNB! Module variants using Nanya SDRAM chips, max temperature limit is +125 °C.

Table 22: Module absolute maximum ratings.


Assembly variants for higher storage temperature range are available on request.
Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage2.55.5VEN6347QI and EP53F8QI datasheets.
3.3VIN supply voltage3.1353.465V3.3V +/- 5%.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.20VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.

Table 23: Recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

  • PCB thickness: 1.6 mm.

  • Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

    

Figure 5: TE0720 module physical dimensions.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2015-10-1203

TE0720-03
-02

TE0720-02
-

01

Prototypes



Table 24: Hardware revision history table.

There is no hardware revision number marking on the module PCB.

Document Change History

Date

Revision

Contributors

Description

  • small document update

v.89John Hartfiel
  • Update power rail section
2017-11-10

v.85

John Hartfiel
  • Replace B2B connector section
2017-09-07

v.84

John Hartfiel
  • Correction of Boot Mode section
2017-08-31

v.83

Jan Kumann
  • Initial document.

--

all

  • --

Table 25: Document change history table.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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