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Clock	Frequency	IC	FPGA	Notes
PLL reference	25 MHz	U3 SiT8208AI	-	Activated by CLK_EN pin of FPGA.
GTX REFCLK0	-	B2B	D5/D6	B2B connector pins: MGT_CLK_0_N: JM3-31 MGT_CLK_0_P: JM3-33 Needs decoupling and differential terminator on base board.
GTX REFCLK1	125 MHz	U2 Si5338	F5/F6	PLL clock 1, default frequency is 125 MHz.
GTX REFCLK2	-	B2B	H5/H6	B2B connector pins: MGT_CLK_2_N: JM3-32 MGT_CLK_2_P: JM3-34 Needs decoupling and differential terminator on base board.
GTX REFCLK3	125 MHz	U2 Si5338	K5/K6	PLL clock 2, default clock is 125 MHz.not configured
Bank 14 input clock	100 MHz	U2 Si5338	F22/E23	PLL clock 0, default frequency is 100 MHz.

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Date	Revision	Contributors	Description
2017-07-20		John Hartfiel	Correction: PLL default output CLKs
2017-06-07	v.55	Jan Kumann	Minor formatting
2017-06-02	Vv.50	Jan Kumann	REV03 specific update.
2017-01-22	Vv.42	Jan Kumann	New block diagram added.
2017-01-13	Vv.38	Jan Kumann	New product images and physical dimension drawings. Formatting improvements and small corrections.
2017-01-12	Vv.21	John Hartfiel	Correction: B2B and FPGA bank location.
2016-12-14	Vv.19	Ali Naseri	TRM revision.
2013-12-02	Vv.1	Antti Lukats, Jon Bean	Initial version.

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