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| Signal | B2B Connector Pin | Function |
|---|---|---|
| DONE | J2-116 | PL configuration completed |
| PROG_B | J2-100 | PL configuration reset signal |
| INIT_B | J2-98 | PS is initialized after a power-on reset |
| SRST_B | J2-96 | System reset |
| MODE0 ... MODE3 | J2-109/J2-107/J2-105/J2-103 | 4-bit boot mode pins For further information about the boot-modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM |
| ERR_STATUS / ERR_OUT | J2-86 / J2-88 | ERR_OUT signal is asserted for accidental loss of ERR_STATUS indicates a secure lockdown lock-down state |
| PUDC_B | J2-127 | Pull-up during configuration (pulled-up to 'PL_1V8') |
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Following boot modes are possible on the TE0803 UltraScale+ MPSoC module by generating the corresponding 4-bit code with pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):
| Boot Mode | Mode Pins [3:0] | MIO Location | Description |
|---|---|---|---|
| JTAG | 0x0 | JTAG | Dedicated PS interface. |
| QSPI32 | 0x2 | MIO[12:0] | Configured on module with dual QSPI Flash Memory. 32-bit addressing. |
configurations. |
supported. | |||
| SD0 | 0x3 | MIO[25:13] | Supports SD 2.0. |
| SD1 | 0x5 | MIO[51:38] | Supports SD 2.0. |
| eMMC_18 | 0x6 | MIO[22:13] | Supports eMMC 4.5 at 1.8V. |
| USB 0 | 0x7 | MIO[52:63] | Supports USB 2.0 and USB 3.0. |
| PJTAG_0 | 0x8 | MIO[29:26] | PS JTAG connection 0 option. |
| SD1-LS | 0xE | MIO[51:39] | Supports SD 3.0 with a required |
Table 9: Selectable boot modes by dedicated boot mode pins
For Functional functional details see see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).
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The TE0803 SoM can be configured with max. 512 MByte Flash Memory memory for configuration and operation.
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The TE0803-01 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte of memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a via 64-bit wide data bus width.
Refer to the Xilinx Zynq UltraScale+ data sheet DS925 to get datasheet DS925 for more information, if the specific package of the Zynq UltraScale+ MPSoC equipped chip on module supports the maximum data transmission rate of 2400 MByte/s.
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Si5338A OTP can only be programmed two times, as different user configurations may required require different setup, TE0803 is normally shipped with blank OTP.
Refer to Si5338A datasheet for more information.
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The control signals have to be asserted on the B2B connector J2, whereby some of the Power - Good - Signals need external pull-up resistors.
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Core voltages and main supply voltages have to reach stable state and their "Power Good" - signals have to be asserted before other voltages like bank 's I/O voltages (VCCOx) can be powered up.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good" - signals are high, meaning that all on-module voltages have become stable and module is properly powered up.
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Table 17: Power rails of the MPSoC module on accessible connectors
Bank Voltages
| Bank | Type | Schematic Name / B2B Connector Pins | Voltage | Reference Input Voltage | Voltage Range |
|---|---|---|---|---|---|
| 25 | HD | VCCO25, pins J3-15, J3-16 |
| User | - |
| Max. 3.3V | ||
| 26 | HD | VCCO26, pins J3-43, J3-44 |
| User | - |
| Max. 3.3V | ||
| 64 | HP | VCCO64, J4-58, J4-106 |
| User | VREF_64, pin J4-88 |
| Max. 1.8V | ||
| 65 | HP | VCCO65, J4-69, J4-105 |
| User | VREF_65, pin J4-15 |
| Max. 1.8V | ||
| 66 | HP | VCCO66, J1-90, J1-120 |
| User | VREF_66, pin J1-108 |
| Max. 1.8V | |||||
| 500 | MIO | PS_1V8 | 1.8V | - | - |
| 501 | MIO | PS_1V8 | 1.8V | - | - |
| 502 | MIO | PS_1V8 | 1.8V | - | - |
| 503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 18: Range of MPSoC module's bank voltages
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All variants are rated for Extended operating temperature range (0 - 100 °C).
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