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On-board Peripherals
System Controller CPLD
The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
See also TE0820 System Controller CPLD pageSection currently not complete.
DDR4 Memory
By default TE0820-02 module has two 16-bit wide Nanya NT5AD256M16B2 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GByte on-board RAM. Different memory sizes are available optionally.
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Date | Revision | Contributors | Description | ||||||||
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| Jan Kumann |
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2017-08-18 | v.7 | John Hartfiel |
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2017-08-07 | v.5 | Jan Kumann | Initial version. | ||||||||
All | Jan Kumann, John Hartfiel |
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