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See Xilinx Virtex-7 datasheet (DS183) for the voltage ranges allowed.
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Power Rails
| Connector / Pin | Voltage | Direction | Notes |
|---|---|---|---|
| J4, pin 2 | 12V (filtered) | Output | 4-wire PWM fan connector suppy voltage |
| J6, pin 2 | 5V (filtered) | Output | Cooling fan M1 supply voltage |
| J8, pin 6 | 3V3PCI | Output | VCCIO CPLD JTAG |
| J9, pin 2 | 1V8 | Output | VCCIO FPGA JTAG |
| J2, pin C35 / C37 | 12V | Output | VCCIO FMC |
| J2, pin D32 | 3V3PCI | Output | VCCIO FMC |
| J2, pin D36 / D38 / D39 / D40 | 3V3FMC | Output | VCCIO FMC |
| J2, pin H1 | VREF_A_M2C | Input | VREF voltage for bank 37 / 38 |
| J2, pin K1 | VREF_B_M2C | Input | VREF voltage for bank 39 |
| J2, pin J39 / J40 | VIO_B_FMC | Input | PL I/O voltage bank 39 (VCCO) |
| J2, pin H40 / G39 / F40 / E39 | FMC_VADJ | Output | VCCIO FMC (fixed to 1.8V) |
| J1, pin A10 / A11 / B8 | 3V3PCI | Input | PCIe interface supply voltage |
| J5, pin 1 / 2 / 3 | 12V | Input | main power supply interface |
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