...
| Lane | Bank | Type | Signal Name | FMC Pin | FPGA Pin |
|---|
| 0 | 117 | GTH | - DP0_M2C_P
- DP0_M2C_N
- DP0_C2M_P
- DP0_C2M_N
| | - MGTHRXP0_117, N4
- MGTHRXN0_117, N3
- MGTHTXP0_117, M2
- MGTHTXN0_117, M1
|
| 1 | 117 | GTH | - DP1_M2C_P
- DP1_M2C_N
- DP1_C2M_P
- DP1_C2M_N
| - J2A-A2
- J2A-A3
- J2A-A22
- J2A-A23
| - MGTHRXP1_117, L4
- MGTHRXN1_117, L3
- MGTHTXP1_117, K2
- MGTHTXN1_117, K1
|
| 2 | 117 | GTH | - DP2_M2C_P
- DP2_M2C_N
- DP2_C2M_P
- DP2_C2M_N
| - J2A-A6
- J2A-A7
- J2A-A26
- J2A-A27
| - MGTHRXP2_117, K6
- MGTHRXN2_117, K5
- MGTHTXP2_117, H2
- MGTHTXN2_117, H1
|
| 3 | 117 | GTH | - DP3_M2C_P
- DP3_M2C_N
- DP3_C2M_P
- DP3_C2M_N
| - J2A-A10
- J2A-A11
- J2A-A30
- J2A-A31
| - MGTHRXP3_117, J4
- MGTHRXN3_117, J3
- MGTHTXP3_117, F2
- MGTHTXN3_117, F1
|
| 4 | 118 | GTH | - DP4_M2C_P
- DP4_M2C_N
- DP4_C2M_P
- DP4_C2M_N
| - J2A-A14
- J2A-A15
- J2A-A34
- J2A-A35
| - MGTHRXP0_118, G4
- MGTHRXN0_118, G3
- MGTHTXP0_118, D2
- MGTHTXN0_118, D1
|
| 5 | 118 | GTH | - DP5_M2C_P
- DP5_M2C_N
- DP5_C2M_P
- DP5_C2M_N
| - J2A-A18
- J2A-A19
- J2A-A38
- J2A-A39
| - MGTHRXP1_118, E4
- MGTHRXN1_118, E3
- MGTHTXP1_118, C4
- MGTHTXN1_118, C3
|
| 6 | 118 | GTH | - DP6_M2C_P
- DP6_M2C_N
- DP6_C2M_P
- DP6_C2M_N
| - J2A-B16
- J2A-B17
- J2A-B36
- J2A-B37
| - MGTHRXP2_118, D6
- MGTHRXN2_118, D5
- MGTHTXP2_118, B2
- MGTHTXN2_118, B1
|
| 7 | 118 | GTH | - DP7_M2C_P
- DP7_M2C_N
- DP7_C2M_P
- DP7_C2M_N
| - J2A-B12
- J2A-B13
- J2A-B32
- J2A-B33
| - MGTHRXP3_118, B6
- MGTHRXN3_118, B5
- MGTHTXP3_118, A4
- MGTHTXN3_118, A3
|
| 8 | 116 | GTH | - DP8_M2C_P
- DP8_M2C_N
- DP8_C2M_P
- DP8_C2M_N
| - J2A-B8
- J2A-B9
- J2A-B28
- J2A-B29
| - MGTHRXP2_116, U4
- MGTHRXN2_116, U3
- MGTHTXP2_116, T2
- MGTHTXN2_116, T1
|
| 9 | 116 | GTH | - DP9_M2C_P
- DP9_M2C_N
- DP9_C2M_P
- DP9_C2M_N
| - J2A-B4
- J2A-B5
- J2A-B24
- J2A-B25
| - MGTHRXP3_116, R4
- MGTHRXN3_116, R3
- MGTHTXP3_116, P2
- MGTHTXN3_116, P1
|
Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).
...
| Lane | Bank | Type | Signal Name | FMC Pin | FPGA Pin |
|---|
| 5 | 118 | GTH | - DP5_M2C_P
- DP5_M2C_N
- DP5_C2M_P
- DP5_C2M_N
| - J2A-A18
- J2A-A19
- J2A-A38
- J2A-A39
| - MGTHRXP1_118, E4
- MGTHRXN1_118, E3
- MGTHTXP1_118, C4
- MGTHTXN1_118, C3
|
| 6 | 118 | GTH | - DP6_M2C_P
- DP6_M2C_N
- DP6_C2M_P
- DP6_C2M_N
| - J2A-B16
- J2A-B17
- J2A-B36
- J2A-B37
| - MGTHRXP2_118, D6
- MGTHRXN2_118, D5
- MGTHTXP2_118, B2
- MGTHTXN2_118, B1
|
| 7 | 118 | GTH | - DP7_M2C_P
- DP7_M2C_N
- DP7_C2M_P
- DP7_C2M_N
| - J2A-B12
- J2A-B13
- J2A-B32
- J2A-B33
| - MGTHRXP3_118, B6
- MGTHRXN3_118, B5
- MGTHTXP3_118, A4
- MGTHTXN3_118, A3
|
| 8 | 116 | GTH | - DP8_M2C_P
- DP8_M2C_N
- DP8_C2M_P
- DP8_C2M_N
| - J2A-B8
- J2A-B9
- J2A-B28
- J2A-B29
| - MGTHRXP2_116, U4
- MGTHRXN2_116, U3
- MGTHTXP2_116, T2
- MGTHTXN2_116, T1
|
| 9 | 116 | GTH | - DP9_M2C_P
- DP9_M2C_N
- DP9_C2M_P
- DP9_C2M_N
| - J2A-B4
- J2A-B5
- J2A-B24
- J2A-B25
| - MGTHRXP3_116, R4
- MGTHRXN3_116, R3
- MGTHTXP3_116, P2
- MGTHTXN3_116, P1
|
Table 8: FPGA to FMC connector MGT lanes overview.
...
There is also a I2C interface between the System Controller CPLD and the DDR3 SDRAM memory:
| Interface signals schematic name | System Controller CPLD pin | DDR3 memory interface pin |
|---|
| DDR3_SDA | Bank 2, pin 48 | Pin 200 (3V3PCI pull-up) |
| DDR3_SCL | Bank 2, pin 49 | Pin 202 (3V3PCI pull-up) |
Table 10: I2C-interface between SC CPLD and DDR3 SDRAM memory.
...