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Table of Contents
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Overview
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Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation. |
The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
Key Features
Industrial-grade Xilinx Zynq-7000 SoC (XC7Z015, XC7Z030)
- Rugged for shock and high vibration
- 2 × ARM Cortex-A9
- 10/100/1000 Mbps Ethernet transceiver PHY
- MAC address EEPROM
- 32-bit wide 1GB DDR3 SDRAM
- 32 MByte quad SPI Flash memory
- Programmable clock generator
- Transceiver clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 4 GTP/GTX (high-performance transceiver) lanes
- GTP/GTX (high-performance transceiver) clock input
- USB 2.0 high-speed ULPI transceiver
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Figure 1: TE0715 block diagram.
Main Components
Figure 2: TE0715 main components.
- 1. Xilinx Zynq-7000 all programmable SoC, U5
- 2. System Controller CPLD, U26
- 3. Programmable quad clock generator , U10
- 4. 10/100/1000 Mbps Ethernet PHY, U7
- 5. 4 Gbit DDR3L SDRAM (1.35 V), U12 and U13
- 6. Hi-speed USB 2.0 ULPI transceiver, U6
- 7a. B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 7b. B2B connector Samtec Razor Beam™ LSHM-150, JM2
- 7c. B2B connector Samtec Razor Beam™ LSHM-130, JM3
- 8. 32-MByte quad SPI Flash memory, U14
- 9. Low-power RTC with battery backed SRAM, U16
- 10. 4A PowerSoC DC-DC converter, U1
- 11. Green LED (DONE), D2
- 12. Red LED (SC), D3
- 13. Green LED (MIO7), D4
- 14. 2-bit bidirectional 1-MHz I2C bus voltage-level translator, U20
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Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
...
Download PDF version of this document.
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Table of Contents
|
Overview
Scroll Only (inline) |
---|
Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation. |
The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GB of DDR3 SDRAM, 32MB of SPI flash memory, gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
Key Features
Industrial-grade Xilinx Zynq-7000 (XC7Z015, XC7Z030) SoC
- Rugged for shock and high vibration
- 2 × ARM Cortex-A9
- 10/100/1000 Mbps Ethernet transceiver PHY
- MAC address EEPROM
- 32-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Transceiver clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 4 GTP/GTX (high-performance transceiver) lanes
- GTP/GTX (high-performance transceiver) clock input
- USB 2.0 high-speed ULPI transceiver
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Main Components
- 1. Xilinx Zynq-7000 all programmable SoC, U5
- 2. System Controller CPLD, U26
- 3. Programmable quad clock generator , U10
- 4. 10/100/1000 Mbps Ethernet PHY, U7
- 5. 4 Gbit DDR3L SDRAM (1.35 V), U12 and U13
- 6. Hi-speed USB 2.0 ULPI transceiver, U6
- 7a. B2B connector Samtec Razor Beam™ LSHM-150, JM1
- 7b. B2B connector Samtec Razor Beam™ LSHM-150, JM2
- 7c. B2B connector Samtec Razor Beam™ LSHM-130, JM3
- 8. 32-MByte quad SPI Flash memory, U14
- 9. Low-power RTC with battery backed SRAM, U16
- 10. 4A PowerSoC DC-DC converter, U1
- 11. Green LED (DONE), D2
- 12. Red LED (SC), D3
- 13. Green LED (MIO7), D4
- 14. 2-bit bidirectional 1-MHz I2C bus voltage-level translator, U20
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Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Si5338 OTP NVM | Default settings pre-programmed | OTP not re-programmable after delivery from factory |
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the SoC's I/O bank and B2B connector:
Table 1: Initial delivery state of programmable devices on the module.
Boot Process
By default the TE-0715 supports quad SPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.
MODE Signal State | Boot Mode |
---|---|
High or open | QSPI |
Low or ground | SD Card |
Table 2: Boot MODE signal description.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the SoC's I/O bank and B2B connector:
Bank | Type | B2B | Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|---|---|---|
13 | HR | JM1 | 48 | User | Supported voltages from 1.2V to 3.3V. | |||
34 | HR/HP | JM2 | 18 | User | TE0715-xx-15 has no HP banks, banks 34 and 35 are HR banks on this module! Banks 34 and 35 on TE0715-xx-30 are HP banks and support voltages from 1.2V to 1.8V. | |||
35 | HR/HP | JM2 | 50 | User | As above. | |||
34 | HR/HP | JM3 | 16 | User | As above. | |||
500 | MIO | JM1 | 8 | 3.3V | - | |||
501 | MIO | JM1 | 6 | 1.8V | - | |||
112 | GT | JM3 | 4 lanes | N/A | - | |||
112 | GT CLK | JM3 | 1 differential input | N/A | NB! AC coupling capacitors on baseboard required. |
Table 3: General overview of board to board I/O signals.
For detailed information about the pin For detailed information about the pin out, please refer to the Pin-out Table.
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
...
JTAG Signal
...
B2B Connector Pin
...
Note |
---|
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
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System Controller I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
...
No hard wired function on PCB, when forced low pulls POR_B low to
emulate power on reset.
...
Active low reset, gated to POR_B.
...
On-board LEDs
...
D2
...
Green
...
DONE
...
Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL is configured.
This LED will not operate if the SC can not power on the 3.3V output
rail that also powers the 3.3V circuitry on the module.
...
D3
...
Red
...
SC
...
D4
...
Green
...
MIO7
...
User controlled, default OFF (when PS7 has not been booted).
MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
---|---|---|---|---|---|
0 | 112 | GTX |
|
|
|
1 | 112 | GTX |
|
|
|
2 | 112 | GTX |
|
|
|
3 | 112 | GTX |
|
|
|
Table 4: MGT lanes.
Below are listed MGT banks reference clock sources.
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
MGT_CLK0_P | 112 | B2B, JM3-33 | MGTREFCLK0P_112, U9 | Supplied by the carrier board. |
MGT_CLK0_N | 112 | B2B, JM3-31 | MGTREFCLK0N_112, V9 | Supplied by the carrier board. |
MGT_CLK1_P | 112 | U10, CLK2A | MGTREFCLK1P_112, U5 | On-board Si5338A. |
MGT_CLK1_N | 112 | U10, CLK2B | MGTREFCLK1N_112, V5 | On-board Si5338A. |
Table x: MGT reference clock sources.
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
JTAG Signal | B2B Connector Pin |
---|---|
TMS | JM2-93 |
TDI | JM2-95 |
TDO | JM2-97 |
TCK | JM2-99 |
Table 5: MGT lanes.
Note |
---|
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
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System Controller I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | Default Configuration |
---|---|---|---|
EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
NOSEQ | - | - | No function. |
RESIN | Input | Reset | Active low reset, gated to POR_B. |
JTAGEN | Input | JTAG Select | Low for normal operation. |
Table 6: System Controller CPLD I/O pins.
Quad SPI Interface
Quad SPI Flash (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
Zynq SoC's MIO | Signal Name | U5 Pin |
---|---|---|
1 | SPI0_CS | 1 |
2 | SPI0_DQ0/MIO2 | 5 |
3 | SPI0_DQ1/MIO3 | 2 |
4 | SPI0_DQ2/MIO4 | 3 |
5 | SPI0_DQ3/MIO5 | 7 |
6 | SPI0_SCK | 6 |
Table 3: Quad SPI interface signals and connections.
Clocking
Clock Signal | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25.000000 MHz | U9 | - | - |
USB PHY reference | 52.000000 MHz | U15 | - | - |
PLL reference | 25.000000 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
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Default MIO Mapping
MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | |
---|---|---|---|---|---|---|---|---|
0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | |
1 | QSPI0 | - | SPI Flash-CS | 28..39 | USB0 | - | ULPI | |
2 | QSPI0 | - | SPI Flash-DQ0 | 40 | SDIO0 | JM1-27 | B2B | |
3 | QSPI0 | - | SPI Flash-DQ1 | 41 | SDIO0 | JM1-25 | B2B | |
4 | QSPI0 | - | SPI Flash-DQ2 | 42 | SDIO0 | JM1-23 | B2B | |
5 | QSPI0 | - | SPI Flash-DQ3 | 43 | SDIO0 | JM1-21 | B2B | |
6 | QSPI0 | - | SPI Flash-SCK | 44 | SDIO0 | JM1-19 | B2B | |
7 | GPIO | - | Green LED D4 | 45 | SDIO0 | JM1-17 | B2B | |
8 | QSPI0 | - | SPI Flash-SCKFB | 46 | GPIO | - | Ethernet PHY LED2 INTn Signal. | |
9 | JM1-91 | B2B | 47 | GPIO | - | RTC Interrupt | ||
10 | JM1-95 | B2B | 48 | I2C1 | - | SCL on-board I2C | ||
11 | JM1-93 | B2B | 49 | I2C1 | - | SDA on-board I2C | ||
12 | JM1-99 | B2B | 50 | GPIO | - | ETH0 Reset | ||
13 | JM1-97 | B2B | 51 | GPIO | - | USB Reset | ||
14 | UART0 | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
15 | UART0 | JM1-85 | B2B | 53 | ETH0 | - | MDIO |
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Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3
Clocking
...
PS CLK
...
33.3333 MHz
...
U11
...
PS_CLK
...
PS subsystem main clock.
...
ETH PHY reference
...
25.000000 MHz
...
U9
...
-
...
USB PHY reference
...
52.000000 MHz
...
U15
...
-
...
PLL reference
...
25.000000 MHz
...
U18
...
-
...
GT REFCLK0
...
-
...
B2B
...
U9/V9
...
Externally supplied from baseboard.
...
GT REFCLK1
...
125 MHz
...
U10 Si5338
...
U5/V5
...
Default clock is 125 MHz.
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Default MIO Mapping
...
Ethernet PHY LED2
INTn Signal.
...
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Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).
Ethernet PHY connection
...
Can be routed via PL to any free PL I/O pin in B2B connector.
This LED is connected to PL via level-shifter implemented in
system controller CPLD.
...
By default the PHY address is strapped to 0x00, alternate
configuration is possible.
...
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USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 5225.000000 MHz oscillator (U15U9), the 125MHz output clock signal CLK_125MHZ is connected to the IN5 pin of the PLL chip (U10).
USB Ethernet PHY connection
PHY Pin | ZYNQ PinPS | B2B NameZYNQ PL | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
REFCLK | - | - | 52.000000 MHz from on board oscillator (U15). |
REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. |
RESETB | MIO51 | - | Active low reset. |
CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
ID | - | OTG_ID | For an A-device connect to the ground, for a B-device leave floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
...
PLL
...
Boot Process
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.
...
MODE Signal State
...
High or open
...
QSPI
...
Low or ground
...
SD Card
On-board Peripherals
32 MByte Quad SPI Flash Memory
On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Note |
---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Processing System (PS) Peripherals
...
Temperature compensated RTC.
...
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
...
IN1/IN2
...
Externally supplied
...
Needs decoupling on base board.
...
IN3
...
25.000000 MHz
...
Fixed input clock.
...
IN4
...
-
...
-
...
IN5/IN6
...
125MHz
...
Ethernet PHY output clock.
...
CLK0
...
-
...
Not used, disabled.
...
CLK1
...
-
...
Not used, disabled.
...
CLK2 A/B
...
125MHz
...
MGT reference clock 1.
...
CLK3A
...
-
...
Bank 34 clock input, default disabled, User clock.
...
CLK3B
...
-
...
Not used, disabled.
MAC Address EEPROM
...
MDC/MDIO | MIO52, MIO53 | - | - |
LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
LED2/Interrupt | MIO46 | - | - |
CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
RESETn | MIO50 | - | - |
RGMII | MIO16..MIO27 | - | - |
SGMII | - | - | Routed to B2B connector JM3. |
MDI | - | - | Routed to B2B connector JM1. |
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USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 52.000000 MHz oscillator (U15).
USB PHY connection
PHY Pin | ZYNQ Pin | B2B Name | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
REFCLK | - | - | 52.000000 MHz from on board oscillator (U15). |
REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. |
RESETB | MIO51 | - | Active low reset. |
CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
ID | - | OTG_ID | For an A-device connect to the ground, for a B-device leave floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for host or device modes. A mini-USB connector can be used for USB device mode. A micro-USB connector can be used for device mode, OTG mode or host mode.
I2C Interface
On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:
I2C Device | I2C Address | Notes |
---|---|---|
EEPROM | 0x50 | |
RTC | 0x6F | |
Battery backed RAM | 0x57 | Integrated into RTC. |
PLL | 0x70 |
On-board Peripherals
DDR Memory
TE0715 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Note |
---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
I/O | Default Frequency | Notes |
---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25.000000 MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, User clock. |
CLK3B | - | Not used, disabled. |
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
On-board LEDs
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Power and Power-On Sequence
...
* TBD - To Be Determined soon with reference design setup.
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.
...
All dimensions are given in millimeters.
Weight
26 g - Plain module
8.8 g - Set of bolts and nutsFigure 3: TE0715 physical dimensions.
Revision History
Hardware Revision History
...
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Figure 4: TE0715 hardware revision number.
Document Change History
Date | Revision | Contributors | Description |
---|---|---|---|
2017-06-07 | v.64 | Jan Kumann | Minor formatting |
2017-03-02 | Vv.59 | Thorsten Trenz | Corrected boot mode table |
2017-02-10 | Vv.58 | Thorsten Trenz | Corrected PLL initial delivery state |
2017-01-25 | Vv.55
| Jan Kumann | New block diagram. |
2017-01-14 | Vv.50 | Jan Kumann | Product revision 04 images added. Formatting changes and small corrections. |
2016-11-15 | Vv.45 | Thorsten Trenz | Added B2B Connector section. |
2016-10-18 | Vv.40 | Ali Naseri | Added table "power rails". |
2016-06-28 | Vv.38
| Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann | New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pin-out Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added. |
2016-04-27 | Vv.33 | Thorsten Trenz, Emmanuel Vassilakis | Added table "Recommended Operating Conditions". Storage Temperature edited. |
2016-03-31 | Vv.10 | Philipp Bernhardt, Antti Lukats | Initial version. |
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Boot mode pin description.