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Template Revision 1.0
Basic Notes
 - export PDF to download, if vivado revision is changed!
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General Design description
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Key Features

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  • PetaLinux
  • SD
  • ETH
  • USB
  • U2C
  • RTC

Revision History

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DateVivadoProject BuiltAuthorsDescription
2017-09-222017.2te0715-test_board-vivado_2017.2-build_02_20170922131837.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170922131853.zip
John Hartfielinitial release

Release Notes and Know Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

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SoftwareSoftwareVersionNote
Vivado2017.2needed
SDK2017.2needed
PetaLinux2017.2needed

Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

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Additional HardwareNotes
USB Cable  for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

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  1. Prepare HW like described on section programming
  2. Connect UART USB (most cases same as JTAG)
  3. Power On PCB

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    1. User Name: root
    2. Password: root

Vivado HW Manager 

MGT Reference CLK Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.

MGT CLK is configured to 125MHz by default, FCLK is not configured by default.

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System Design - Vivado

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Description currently not available.

Block Design

Image Added

Constrains

Basic module constrains

 

Block Design

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Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
Code Block
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title_i_unused_io.xdc
linenumberstrue
collapsetrue
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

 

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title_i_io.xdc
linenumberstrue
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set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

Description currently not available.

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Description currently not available.

Config

No changes.

U-Boot

No changes.

Device Tree

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/include/ "system-conf.dtsi"
/ {
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/* default */

/* ETH PHY */
&gem0 {

    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <0>;
    };
};


/* USB PHY */
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {        // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
   };

};


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  • RTC_DRV_ISL12022

Rootfs

No changes.

Applications

No additional applications.

Additional Software

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No additional software is needed.

Appx. A: Change History and Legal Notices

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