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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2021.2
  • PetaLinux
  • SD
  • ETH
  • MAC from EEPROM
  • USB
  • I2C
  • RTC
  • FMeter
  • Modified FSBL (some additional outputs and SI5338 reconfiguration)
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
Manuela Strücker
  • 2021.2 update
Manuela Strücker
  • new Assembly variants
Manuela Strücker
  • update mount function (from busybox to util-linux 2.34)

John Hartfiel/

Manuela Strücker

  • bugfix TE0715_board_files.csv for  TE0715-04-71I33-L ID

John Hartfiel/
Manuela Strücker

  • update to vivado version 2020.2
  • implemented boot.scr file for distro_boot
John Hartfiel
  • bugfix usb reset
  • changes device tree for eeprom mac
  • new variants
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
John Hartfiel
  • Rework Board Part Files (PS)
  • small design changes
  • SI5338 reconfiguration default activated on FSBL
  • update linux startup app
John Hartfiel
  • new assembly variant
John Hartfiel
  • Board Part Bug fix with UART 1
John Hartfiel
  • No Design changes
  • Add FSBL for Flash Programming
John Hartfiel
  • New Web Link on Board Part Files
  • Add optional FSBL Code to reprogram  SI5338
John Hartfiel
  • changed Flash typ on TE0715_board_files.csv
    (older one is not supported on Vivado 2017.2)
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashProgramming QSPI fails with Vivado 2021.2use Vivado 2020.2 or 2019.2 for programming
Timing problems with Frequency countercan be ignored---with 2018-10-01 update
Known Issues



Vitis2021.2needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0715-04-12S-1C04_12s_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-15-1I04_15_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-15-1I304_15_1i_1gbREV041GB32MBNANALow Power DDR 2.5mm connector
TE0715-04-15-1IC04_15_1i_1gbREV041GB32MBNANALow Power DDR. 3M NOVEC coating
TE0715-04-15-2I*04_15_2i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-21C33-A04_12s_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1C04_30_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1I04_30_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1I304_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector
TE0715-04-30-1IA04_30_1i_1gbREV041GB32MBNANALow Power DDR. Micron Flash
TE0715-04-30-3E04_30_3e_1gbREV041GB32MBNANALow Power DDR
TE0715-04-51I33-A04_15_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-51I33-AN04_15_1i_1gbREV041GB32MBNANALow Power DDR. 3M NOVEC coating
TE0715-04-51I33-L04_15_1i_1gbREV041GB32MBNANALow Power DDR 2.5mm connector
TE0715-04-52I33-A04_15_2i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71C33-A04_30_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71I33-A04_30_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71I33-L04_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector
TE0715-04-73E33-A04_30_3e_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1IY04_30_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-51I33-AY04_15_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-52I33-AY04_15_2i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71C33-AY04_30_1c_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71I33-AY04_30_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71I33-LY04_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector, without RTC
TE0715-04-S00304_30_1i_1gbREV041GB32MBNANACAO: Low Power DDR

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Additional Hardware


For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources


<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files

Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration<project folder>\misc\sd\Additional Initialization Script for Linux (working from sd card only)
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start  design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  8. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

TE0715-0x-30-xx  only: HP IO Banks max power supply voltage is 1.8V.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Optional for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0715 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.scr and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    • optional: use startup script for SD
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg | grep tty  (UART is *USB1)

  2. Linux Console:

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 1 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
  4. Option Features
    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • scripts
      • add script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager 

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
  • Monitoring:
    • Si5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL → 50MHz on delivered configuration, see FSBL description).
Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

PS Interfaces


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]
# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks mgt_clk1_clk_p]
set_false_path -from [get_clocks mgt_clk1_clk_p] -to [get_clocks clk_fpga_0]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


TE modified 2021.2 FSBL


  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • SI5338 Configuration


TE modified 2021.2 FSBL


  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description




Start with petalinux-config -c u-boot


  • CONFIG_ENV_OVERWRITE=y                       (used to overwrite environment parameter)
  • CONFIG_ENV_IS_IN_FAT=y                           (needed to boot from SD card)
  • CONFIG_ENV_IS_IN_SPI_FLASH=y                  (needed to boot from QSPI flash)
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x1920000   (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)

Device Tree (system-user.dtsi in device-tree and uboot-device-tree)

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
/*------------------- default --------------------*/
/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
/*--------------------- ETH PHY ------------------*/
&gem0 {
    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <0>;
/*---------------------- USB PHY -----------------*/ 
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
/*---------------------- I2C ---------------------*/
// i2c PLL: 0x70, i2c eeprom: 0x50
&i2c1 {
  rtc@6F {                      // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
  eeprom: eeprom@50 {           //MAC EEPROM
    compatible = "atmel,24c08";
    reg = <0x50>;

FSBL patch

Must be add manually --> work in progress


Start with petalinux-config -c kernel




Start with petalinux-config -c rootfs


  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y         (for web server app)
  • CONFIG_usbutils=y
  • CONFIG_util-linux-umount=y      (uses mount/umount function from util-linux instead of busybox)
  • CONFIG_util-linux-mount=y


See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"


Script App to load from SD Card if available.


Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software


File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History" of this page and select older document revision number.

DateDocument Revision



  • Release 2021.2
2021-12-16v.39Manuela Strücker
  • new Assembly variants
2021-06-16v.38Manuela Strücker
  • changed mount/umount function in PetaLinux
2021-05-31v.37John Hartfiel
  • Design update (bugfix csv file)


v.36Manuela Strücker
  • Release 2020.2
  • added boot.scr for distro boot
2020-06-10v.33John Hartfiel
  • Release 2019.2
2019-05-09v.32John Hartfiel
  • Release 2018.3
  • FSBL Rework
  • Script rework
  • some optional features
2018-10-01v.31John Hartfiel
  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style


v.30John Hartfiel
  • New assembly variant


v.29John Hartfiel
  • Bugfix Board Part Files
2018-02-13v.28John Hartfiel
  • Release 2017.4
2017-11-10v.22John Hartfiel
  • Design Update with new options
  • Add Si5338 section
  • Update FSBL section


John Hartfiel
  • Download Update
2017-10-19v.20John Hartfiel
  • Document style update
2017-10-06v.18John Hartfiel
  • Text correction
  • Update Launch section
  • Supported PCBs
2017-10-02v.14John Hartfiel
  • Document update on Prebuilt section
John Hartfiel
  • Initial Release 2017.2
Document change history.

Legal Notices

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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