Page History
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Date | Vivado | Project Built | Authors | Description |
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2017-09-22 | 2017.2 | te0715-test_board-vivado_2017.2-build_02_20170927084628.zip20170927143412 te0715-test_board_noprebuilt-vivado_2017.2-build_02_2017092708464120170927143427.zip | John Hartfiel | initial release |
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch. TE0715-0x-30-xx only: HP IO Banks max power supply voltage is 1.8V. |
Programming
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
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- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
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- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
- Set radix from VIO signals to unsigned integer.
MGT CLK is configured to 125MHz by default, FCLK is not configured by default.
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System Design - Vivado
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<!-- Description of Block Design, Constrains... BD Pictures from Export... --> |
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Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\filesNo additional applications.
Additional Software
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<!-- Add Description for other Software, for example SI CLK Builder ... --> |
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Date | Document Revision | Authors | Description | ||||||||||||||||||||||
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| Work in progressRelease 2017.2 | ||||||||||||||||||||||
2017-09-11 | v.1 |
| Initial release | ||||||||||||||||||||||
All |
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Overview
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