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Only on ZIP file with Prebuilt content.

File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Diverse Reports

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Report files in different formats

Hardware-Platform-Specification-Files

*.hdf

Exported Vivado Hardware Specification for SDK/HSI and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

HTML
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Basic Design Steps
Add/ Remove project specific 
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