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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Table of contents
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| Info |
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2 Firmware variants with swapped external reset input and output direction are available. See Watchdog section of this document. Firmware (SC729_rev02plus03_default_teb0729_02_plus.jed) for J2-89 as external reset output and J2-91 as external reset input will be used as default firmware. |
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Power
3.3V (EN_3V3) is enabled on power up.
Boot Mode
Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.
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Firmware Variants:
Figure1: Firmware (SC729_rev02org_03_teb0729_02_org.jed) for TEB0729 without HW modification,
|  Figure2: Firmware (SC729_rev02plus_03_default_teb0729_02_plus.jed) for TEB0729 with HW modification,
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| IOs | B2B | Direction | Description |
|---|---|---|---|
| nRST | J2-89 | ininout | Main Reset to module |
| nRST_IN | J2-91 | out | Main reset to carrier and PS_POR_B for approx. 1,9 us. |
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| IOs | B2B | Direction | Description |
|---|---|---|---|
| nRST | J2-89 | out | Main reset to carrier and PS_POR_B |
| nRST_IN | J2-91 | ininout | Main Reset to module |
1V Power supply:
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CPLD controlled WD on power up until FPGA takes control via WE_EN and WD_HIT input. CPLD WDI pulse frequency is set to approx. 1ms (Pulse width tw(CPLD)=507us )
nRST_IN is set to GND on power up for short time periode
FPGA Control:
WD_HIT pulse will be forwarded to WDI pin, if WE_EN is high and min 16 WD_HIT from FPGA was detected. To disable FPGA Control, set WD_EN to low.
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| Modus | Condition |
|---|---|
| Slow Blink | If PS_POR_B is low and appr. 16s after PS_POR_B goes up |
| FPGA_IO | User defined, appr. 16s after PS_POR_B goes up and as long as PS_POR_B is high |
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Info: On TEB0729, signal is connected to XMOD LED.
Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV02 to REV03
- Add power up Watchdog main reset from CPLD
CPLD REV01 to REV02
- Bugfix for TE0729-REV02 Watchdog support
- Add 2 Variants for TEB0729-REV02 and TE0729-REV02_MOD support
- Change Pin FGPA_IO direction
- Change Pin BOARD_STAT output configuration
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV02REV03 | REV02/REV02plus/REV03 |
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| 2017-08-31 | v.14 | REV02 | REV02/REV02plus | John Hartfiel | |||||||||||||||||||||||
| 2017-08-23 | v.13 | REV02 | REV02/REV02plus | John Hartfiel |
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| 2017-06-07 | REV02 | REV02/REV02plus |
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