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With the TEBA0841 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as LVDS-differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.
Following table gives a summary of the available I/O's, interfaces and LVDS-differential pairs of the B2B connectors JB1, JB2 and JB3:
B2B Connector | Interfaces | Count of I/O's | Notes | |||
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JB1 | User I/O | 48 42 single ended or 24 differential | - | GbE MagJack MDI | 821 differential | - |
SD IO | 6 | - | ||||
MIO | 8 | - | ||||
SoM control signals | 51- | 'BOOTMODE' | ||||
JB2 | MGT lanes | 8 differential pairs, 4 lanes | JB3 | GbE PHY RGMII | 18 | - |
MGT reference input clock | 1 differential pair | |||||
USB2.0 (OTG , and device and host mode) | 54 | - | ||||
JB2 | User I/O | 18 42 single ended 21 differential | - | 48 single ended or 24 differential | - | |
JTAG | 4 | -SoM control signals | ||||
Red user LED | 1 | - | ||||
MagJack J3 LED's | 2 | - |
Table 1: General overview Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
On-board
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Pin Header
The TE0706 TEBA0841 Carrier Board has and a 50-pin IDC male connector J5 and soldering pads as place-holder to mount a VG96 connectors J6 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these connectorspin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as differential pairs.
Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the connectors J5 and J6pin headers:
On-board ConnectorPin Header | Control Signals and Interfaces | Count of I/O's | Notes | ||
---|---|---|---|---|---|
J17 | User I/O | 18 42 single ended or 21 differential | - | ||
J20 | User I/O | 42 14 single ended or 7 21 differential | - | ||
J3 | 8 | - | |||
MagJack J2 LED's | 2 | - | |||
JTAG | 4 | J6 | User I/O | 82 single ended or 41 differential | - |
SoM control signals | 2 | 'PGOODRESIN', 'NOSEQ' |
Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
JTAG Interface
JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.
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JTAG Signal
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B2B Connector Pin
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Table 3: JTAG interface signals.
UART Interface
UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
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Table 4: UART interface signals.
I²C Interface
One of the SoM's I²C interface is routed to the on-board connector J5 and is available to the user for general purposes:
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Table 5: I²C interface signals.
SD IO Interface
The SD IO interface of the mounted SoM is routed to the on-board Texas Instruments TXS02612 SDIO port expander U4. This IC provides a necessary VDD/VCCIO translation between the MicroSD Card socket J4 (3.3V) and the SoM's Zynq device MIO-bank (1.8V):
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Table 6: SD IO interface signals.
USB2.0 Interface
TE0706-02 board has one physical USB2.0 type A socket J7, the differential data signals of the USB2.0 socket are routed to the B2B connector JB3, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.
There is also the option to equip the board with a Micro USB 2.0 type B (receptacle) socket (J8) to the board as alternative fitting option. With this fitting option (Micro USB2.0 type B), the USB2.0 interface can also be used for Device mode, OTG and Host Modes.
For USB2.0 Host mode, the Carrier Board is additionally equipped with a power distribution switch U5 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.
Following table gives an overview of the USB2.0 interface signals:
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JB2-48
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Table 7: USB2.0 interface signals and connections.
Gigabit Ethernet Interface
The TE0706 Carrier Board is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U6), which provides in conjunction with the Gigabit Ethernet MagJack J2 a 1000Base-T Ethernet (GbE) interface. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied by on-board 25MHz oscillator (U7).
The GbE MegJack J2 has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the GbE PHY.
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JB3-47,
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Reduced Gigabit Media Independent Interface.
12 pins.
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Serial Gigabit Media Independent Interface.
Not connected.
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Media Dependent Interface.
Connected to Gigabit Ethernet MagJack J2.
BOOTMODE' | |||
MGT reference input clock | 1 differential pair | AC decoupled on-board (100 nF capacitator) | |
MIO | 2 | user IO (configurable as UART for example) | |
J4 | SD IO | 6 | 3.3V and 1.8V voltage level available on header |
Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
SFP+ Connector
On the TEBA0841 carrier board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).
The RX-/TX-data-lanes are connected to B2B-connector JB2, the control-lines are connected to module's IO-pins on B2B-connector JB1 (MIO0-bank-pins in standard TE module's pin-assignment).
On this SFP+ connector, at both 4 x 5 SoMs TE0741 and TE0841 MGT-lane 3 is accessible.
The pin-assignment of the SFP connector is in detail as fellows:
SFP+ pin | Pin Schematic Name | B2B | FPGA Direction | Description | Note |
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Transmit Data + (pin 18) | MGT_TX3_P | JB2-26 | Output | - | |
Transmit Data - (pin 19) | MGT_TX3_N | JB2-28 | Output | - | |
Receive Data + (pin 13) | MGT_RX3_P | JB2-25 | Input | - | |
Receive Data - (pin 12) | MGT_RX3_N | JB2-27 | Input | - | |
Receive Fault (pin 2) | MIO10 | JB1-96 | Input | Fault / Normal Operation | - |
Receive disable (pin 3) | - | - | Output | SFP Enabled / Disabled | connected to GND |
MOD-DEF2 (pin 4) | MIO13 | JB1-98 | Input | Module present / not present | 3.3V pull-up, (usable I²C SDA/SCL-line) |
MOD-DEF1 (pin 5) | MIO12 | JB1-100 | Output | 2-wire Serial Interface clock | 3.3V pull-up, (usable I²C SDA/SCL-line) |
MOD-DEF0 (pin 6) | MIO11 | JB1-94 | BiDir | 2-wire Serial Interface data | - |
RS0 (pin 7) | SFP0_RS0 | - | Output | Full RX bandwidth | - |
LOS (pin 8) | MIO0 | JB1-88 | Input | Loss of receiver signal | - |
RS1 (pin 9) | SFP0_RS1 | - | Output | Reduced RX bandwidth | - |
Table 1: SFP+ connector pin-assignment
Looped-backed MGT-Lanes on B2B Connector JB1 and JB2
The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification.
The MGT lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:
MGT Lane | B2B TX Differential Pair | B2B RX Differential Pair | B2B Pins Bridged |
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MGT-lane 0 | JB2-8 (MGT_TX0_N) JB2-10 (MGT_TX0_P) | JB2-7 (MGT_RX0_N) JB2-9 (MGT_RX0_P) | JB2-7 to JB2-8 JB2-9 to JB2-10 |
MGT-lane 1 | JB2-14 (MGT_TX1_N) JB2-16 (MGT_TX1_P) | JB2-13 (MGT_RX1_N) JB2-15 (MGT_RX1_P) | JB2-13 to JB2-14 JB2-15 to JB2-16 |
MGT-lane 2 | JB2-20 (MGT_TX2_N) JB2-22 (MGT_TX2_P) | JB2-19 (MGT_RX2_N) JB2-21 (MGT_RX2_P) | JB2-19 to JB2-20 JB2-21 to JB2-22 |
MGT-lane 7 | JB1-3 (MGT_TX7_P) JB1-5 (MGT_TX7_N) | JB1-9 (MGT_RX7_P) JB1-11 (MGT_RX7_N) | JB1-3 to JB1-9 JB1-5 to JB1-11 |
MGT-lane 6 | JB1-15 (MGT_TX6_P) JB1-17 (MGT_TX6_N) | JB1-21 (MGT_RX6_P) JB1-23 (MGT_RX6_N) | JB1-15 to JB1-21 JB1-17 to JB1-23 |
Table 2: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.
Note |
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Note: The mounted TE 4 x 5 SoMs have different schematic net-names of the differential signaling pairs of the MGT-lanes. See Schematic of the particular SoM. |
JTAG Interface
JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.
JTAG Signal | B2B Connector Pin | XMOD Header JX1 | Pin Header J3 | Note |
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TCK | JB3-100 | JX1-4 | J3-4 | - |
TDI | JB3-96 | JX1-10 | J3-10 | - |
TDO | JB3-98 | JX1-8 | J3-8 | - |
TMS | JB3-94 | JX1-12 | J3-12 | - |
Table 3: JTAG interface signals.
UART Interface
UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
UART Signal Schematic Name | B2B | XMOD Header JX1 | Pin Header J3 | Note |
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MIO14 | JB1-91 | JX1-7 | J3-7 | UART-RX (receive line) |
MIO15 | JB1-86 | JX1-3 | J3-3 | UART-TX (transmit line) |
Table 4: UART interface signals.
SD IO Interface
The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:
SD IO Signal Schematic Name | B2B | Pin Header J4 | Note |
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SD_DAT0 | JB1-24 | J4-8 | SD IO data |
SD_DAT1 | JB1-22 | J4-10 | SD IO data |
SD_DAT2 | JB1-20 | J4-9 | SD IO data |
SD_DAT3 | JB1-18 | J4-7 | SD IO data |
SD_CLK | JB1-28 | J4-4 | SD IO clock |
SD_CMD | JB1-26 | J4-3 | SD IO command |
Table 6: SD IO interface signals.
USB2.0 Interface
TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.
With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.
Following table gives an overview of the USB2.0 interface signals:
USB2.0 Signal Schematic Name | B2B | Connected to | Note |
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OTG_N | JB2-48 | J10-2 | USB2.0 data |
OTG_P | JB2-50 | J10-3 | USB2.0 data |
OTG-ID | JB2-52 | J10-4 | Ground this pin for A-Device (host), left floating this pin for B-Device (peripheral). |
USB-VBUS | JB2-56 | J10-1 | USB supply voltage for Host mode. Not supplied by the Carrier Board. |
Table 7: USB2.0 interface
Table 8: GbE interface signals and connections.
RJ45 Gigabit Ethernet MagJack J3
The TE0706-02 carrier board is also equipped with a second Gigabit-Ethernet MagJack J3, which is connected via MDI to the B2B connector JB1.
There is usually a corresponding Gigabit Ethernet PHY on 4 x 5 SoMs (e.g. TE0715 or TE0720), which can be used in conjunction with the baseboard MagJack J3.
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JB1-3
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Table 9: RJ45 GbE MagJack signals and connections.
XMOD FTDI JTAG-Adapter Header
The JTAG interface of the mounted SoM can be accessed via XMOD header JX1 and pin header J3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal.
So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.
Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:
Pin Schematic Name | XMOD Header JX1 Pin | Header J3 Pin |
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B2B | Note | |
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TCK | C (pin 4) |
4 |
JB3-100 | - |
TDO | D (pin 8) |
8 |
JB3-98 | - |
TDI | F (pin 10) |
10 |
JB3-96 | - |
TMS | H (pin 12) |
12 |
JB3-94 | - |
MIO15 | A (pin 3) |
3 | JB1-86 | UART-TX (transmit line) |
MIO14 | B (pin 7) |
7 | JB1-91 | UART-RX (receive line) | |
BOOTMODE | E (pin 9) | 9 | JB1-90 |
usually JTAG select pin | ||||
RESIN | G (pin 11) | 11 | JB3-17 | SoM Reset pin |
CLK0_N | - | 15 | JB2- |
32 | AC decoupled on-board (100 nF capacitator) | |||
CLK0_P | - | 16 | JB2-34 | AC decoupled on-board (100 nF capacitator) |
Table 10: XMOD JTAG/UART header signals and connections.
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