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Table of Contents |
<!-- Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0706 --> |
Refer to https://wiki.trenz-electronic.de/display/PD/TEBA0841+TRM for the current online version of this manual and other available documentation. |
The Trenz Electronic TEBA0841 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi-gigabit transceiver units of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs.
See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 base-board.
Additional assembly options are available for cost or performance optimization upon request.
Figure 1: TEBA0841-01 Block Diagram.
Figure 2: TE0706-02 Carrier Board
Board is shipped in following configuration:
Different delivery configurations are available upon request.
<!-- Connections and Interfaces or B2B Pin's which are accessible by User --> |
With the TEBA0841 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.
Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:
B2B Connector | Interfaces | Count of I/O's | Notes |
---|---|---|---|
JB1 | User I/O | 42 single ended or 21 differential | - |
SD IO | 6 | - | |
MIO | 8 | - | |
SoM control signals | 1 | 'BOOTMODE' | |
JB2 | MGT lanes | 8 differential pairs, 4 lanes | - |
MGT reference input clock | 1 differential pair | ||
USB2.0 (OTG and device mode) | 4 | - | |
JB2 | User I/O | 42 single ended 21 differential | -- |
JTAG | 4 | - | |
Red user LED | 1 | - |
Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
The TEBA0841 Carrier Board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as differential pairs.
Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:
On-board Pin Header | Control Signals and Interfaces | Count of I/O's | Notes |
---|---|---|---|
J17 | User I/O | 42 single ended or 21 differential | - |
J20 | User I/O | 42 single ended or 21 differential | - |
J3 | JTAG | 4 | - |
SoM control signals | 2 | 'RESIN', 'BOOTMODE' | |
MGT reference input clock | 1 differential pair | AC decoupled on-board (100 nF capacitator) | |
MIO | 2 | user IO (configurable as UART for example) | |
J4 | SD IO | 6 | 3.3V and 1.8V voltage level available on header |
Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
On the TEBA0841 carrier board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).
The RX-/TX-data-lanes are connected to B2B-connector JB2, the control-lines are connected to module's IO-pins on B2B-connector JB1 (MIO0-bank-pins in standard TE module's pin-assignment).
On this SFP+ connector, at both 4 x 5 SoMs TE0741 and TE0841 MGT-lane 3 is accessible.
The pin-assignment of the SFP connector is in detail as fellows:
SFP+ pin | Pin Schematic Name | B2B | FPGA Direction | Description | Note |
---|---|---|---|---|---|
Transmit Data + (pin 18) | MGT_TX3_P | JB2-26 | Output | - | |
Transmit Data - (pin 19) | MGT_TX3_N | JB2-28 | Output | - | |
Receive Data + (pin 13) | MGT_RX3_P | JB2-25 | Input | - | |
Receive Data - (pin 12) | MGT_RX3_N | JB2-27 | Input | - | |
Receive Fault (pin 2) | MIO10 | JB1-96 | Input | Fault / Normal Operation | - |
Receive disable (pin 3) | - | - | Output | SFP Enabled / Disabled | connected to GND |
MOD-DEF2 (pin 4) | MIO13 | JB1-98 | Input | Module present / not present | 3.3V pull-up, (usable I²C SDA/SCL-line) |
MOD-DEF1 (pin 5) | MIO12 | JB1-100 | Output | 2-wire Serial Interface clock | 3.3V pull-up, (usable I²C SDA/SCL-line) |
MOD-DEF0 (pin 6) | MIO11 | JB1-94 | BiDir | 2-wire Serial Interface data | - |
RS0 (pin 7) | SFP0_RS0 | - | Output | Full RX bandwidth | - |
LOS (pin 8) | MIO0 | JB1-88 | Input | Loss of receiver signal | - |
RS1 (pin 9) | SFP0_RS1 | - | Output | Reduced RX bandwidth | - |
Table 1: SFP+ connector pin-assignment
The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification.
The MGT lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:
MGT Lane | B2B TX Differential Pair | B2B RX Differential Pair | B2B Pins Bridged |
---|---|---|---|
MGT-lane 0 | JB2-8 (MGT_TX0_N) JB2-10 (MGT_TX0_P) | JB2-7 (MGT_RX0_N) JB2-9 (MGT_RX0_P) | JB2-7 to JB2-8 JB2-9 to JB2-10 |
MGT-lane 1 | JB2-14 (MGT_TX1_N) JB2-16 (MGT_TX1_P) | JB2-13 (MGT_RX1_N) JB2-15 (MGT_RX1_P) | JB2-13 to JB2-14 JB2-15 to JB2-16 |
MGT-lane 2 | JB2-20 (MGT_TX2_N) JB2-22 (MGT_TX2_P) | JB2-19 (MGT_RX2_N) JB2-21 (MGT_RX2_P) | JB2-19 to JB2-20 JB2-21 to JB2-22 |
MGT-lane 7 | JB1-3 (MGT_TX7_P) JB1-5 (MGT_TX7_N) | JB1-9 (MGT_RX7_P) JB1-11 (MGT_RX7_N) | JB1-3 to JB1-9 JB1-5 to JB1-11 |
MGT-lane 6 | JB1-15 (MGT_TX6_P) JB1-17 (MGT_TX6_N) | JB1-21 (MGT_RX6_P) JB1-23 (MGT_RX6_N) | JB1-15 to JB1-21 JB1-17 to JB1-23 |
Table 2: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.
Note: The mounted TE 4 x 5 SoMs have different schematic net-names of the differential signaling pairs of the MGT-lanes. See Schematic of the particular SoM. |
JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.
JTAG Signal | B2B Connector Pin | XMOD Header JX1 | Pin Header J3 | Note |
---|---|---|---|---|
TCK | JB3-100 | JX1-4 | J3-4 | - |
TDI | JB3-96 | JX1-10 | J3-10 | - |
TDO | JB3-98 | JX1-8 | J3-8 | - |
TMS | JB3-94 | JX1-12 | J3-12 | - |
Table 3: JTAG interface signals.
UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
UART Signal Schematic Name | B2B | XMOD Header JX1 | Pin Header J3 | Note |
---|---|---|---|---|
MIO14 | JB1-91 | JX1-7 | J3-7 | UART-RX (receive line) |
MIO15 | JB1-86 | JX1-3 | J3-3 | UART-TX (transmit line) |
Table 4: UART interface signals.
The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:
SD IO Signal Schematic Name | B2B | Pin Header J4 | Note |
---|---|---|---|
SD_DAT0 | JB1-24 | J4-8 | SD IO data |
SD_DAT1 | JB1-22 | J4-10 | SD IO data |
SD_DAT2 | JB1-20 | J4-9 | SD IO data |
SD_DAT3 | JB1-18 | J4-7 | SD IO data |
SD_CLK | JB1-28 | J4-4 | SD IO clock |
SD_CMD | JB1-26 | J4-3 | SD IO command |
Table 6: SD IO interface signals.
TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.
With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.
Following table gives an overview of the USB2.0 interface signals:
USB2.0 Signal Schematic Name | B2B | Connected to | Note |
---|---|---|---|
OTG_N | JB2-48 | J10-2 | USB2.0 data |
OTG_P | JB2-50 | J10-3 | USB2.0 data |
OTG-ID | JB2-52 | J10-4 | Ground this pin for A-Device (host), left floating this pin for B-Device (peripheral). |
USB-VBUS | JB2-56 | J10-1 | USB supply voltage for Host mode. Not supplied by the Carrier Board. |
Table 7: USB2.0 interface signals and connections.
The JTAG interface of the mounted SoM can be accessed via XMOD header JX1 and pin header J3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal.
So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.
Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:
Pin Schematic Name | XMOD Header JX1 Pin | Header J3 Pin | B2B | Note |
---|---|---|---|---|
TCK | C (pin 4) | 4 | JB3-100 | - |
TDO | D (pin 8) | 8 | JB3-98 | - |
TDI | F (pin 10) | 10 | JB3-96 | - |
TMS | H (pin 12) | 12 | JB3-94 | - |
MIO15 | A (pin 3) | 3 | JB1-86 | UART-TX (transmit line) |
MIO14 | B (pin 7) | 7 | JB1-91 | UART-RX (receive line) |
BOOTMODE | E (pin 9) | 9 | JB1-90 | usually JTAG select pin |
RESIN | G (pin 11) | 11 | JB3-17 | SoM Reset pin |
CLK0_N | - | 15 | JB2-32 | AC decoupled on-board (100 nF capacitator) |
CLK0_P | - | 16 | JB2-34 | AC decoupled on-board (100 nF capacitator) |
Table 10: JTAG/UART header signals and connections.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the mounted SoM's 'VCCJTAG' (pin JB2-92). Set the DIP-switch with the setting:
XMOD DIP-switches | Position |
---|---|
Switch 1 | ON |
Switch 2 | OFF |
Switch 3 | OFF |
Switch 4 | ON |
Table 11: XMOD adapter board DIP-switch positions for voltage configuration.
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
<!-- Components on the Module, like Flash, PLL, PHY... --> |
Table below describes DIP-switch S1 settings for configuration of the mounted SoM:
Switch | Signal Name | ON | OFF | Notes |
---|---|---|---|---|
S1-1 | - | - | - | Not connected. |
S1-2 | PROGMODE | JTAG enabled for programing mounted SoM's Zynq-SoC. | JTAG enabled for programing mounted SoM's SC-CPLD. | - |
S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low. | Leave SoM SC CPLD pin 'MODE' open. | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware). |
S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low. | Drive SoM SC CPLD pin 'EN1' high. | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM. |
Table 12: DIP-switch S1 SoM configuration settings.
Figure 3: User DIP-switch S1
Note: The corresponding PL I/O-bank supply-voltages of the 4 x 5 SoM to the selectable base-board voltages VCCIOA, VCCIOB and VCCIOC are depending on the mounted 4 x 5 SoM and varying in order of the used model. Refer to the SoM's schematic for information about the specific pin assignments on module's B2B-connectors regarding the PL I/O-bank supply-voltages and to the 4 x 5 Module integration Guide for VCCIO voltage options. |
The Carrier Board VCCIO for the PL I/O-banks of the mounted SoM are selectable by the jumpers J10, J11 and J12.
Following table describes how to configure the VCCIO of the SoM's PL I/O-banks with jumpers:
Supply Voltage by Jumper | Supply Voltage by 0-Ohm Resistor | Supply Voltage by Connector J6 | ||||
---|---|---|---|---|---|---|
Voltage Level | 1.8V | 3.3V | 1.8V | 3.3V | Variable | |
VCCIOA | J10: 1-2, 3 | J10: 1, 2-3 | - | R20 | J6 pin B32 | |
VCCIOB | J11: 1-2, 3 | J11: 1, 2-3 | R29 | R21 | - | |
VCCIOC | J12: 1-2, 3 | J12: 1, 2-3 | R30 | R22 | J6 pin B1 |
Table 13: VCCIO jumper settings.
Figure 4: Base-board supply-voltages (VCCIOA, VCCIOB, VCCIOC) selection jumpers.
Only one supply-source is allowed to configure the base-board supply-voltages, either by jumper, by 0-Ohm-resistor or by connector J6. If a supply-voltage is configured by 0-Ohm-resistor or connector J6, then the corresponding configuration-jumper has to be removed. There aren't 0-Ohm-resistors and supply-voltages by connector J6 allowed if the corresponding base-board supply-voltage is configured by jumper. Vice versa jumpers and 0-Ohm-resistors have to be removed if supplying corresponding base-board supply-voltage by connector J6.
Note: If supplying base-board supply-voltages by connector J6, the module's internal 3.3V voltage-level on pins 9 and 11 of B2B-connector JB2 has to be reached stable state.
Take care of the VCCO voltage ranges of the particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges. It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM. |
The buffer voltage of the SoM's RTC can be supplied through the header J9 (VBAT-pin). Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.
The Carrier Board's push button S2 is connected to the 'RESIN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.
<!-- If power sequencing and distribution is not so much, you can join both sub sections together --> |
The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
5VIN | TBD* |
Table 14: Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence. |
The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:
Figure 5: Board power distribution diagram.
The voltage direction of the power rails is from board and on-board connectors' view:
Module Connector (B2B) Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
JB1 | 3.3V | Out | 2, 4, 6, 14, 16 | 3.3V module supply voltage |
VCCIOA | Out | 10, 12 | PL IO-bank VCCIO | |
M1.8VOUT | In | 40 | 1.8V module output voltage | |
VBAT | Out | 80 | RTC buffer voltage | |
JB2 | 1.8V | Out | 2, 4 | 1.8V module supply voltage |
VCCIOB | Out | 6 | PL IO-bank VCCIO | |
VCCIOC | Out | 8, 10 | PL IO-bank VCCIO | |
M3.3VOUT | In | 9, 11 | 3.3V module output voltage | |
VCCJTAG | In | 92 | 3.3V JTAG VCCIO | |
JB3 | USB-VBUS | Out | 56 | USB Host supply voltage |
Table 15: Power pin description of B2B module connector.
On-board Connector Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J5 | 3.3V | Out | 6, 45 | 3.3V module supply voltage |
M3.3VOUT | In | 5, 46 | 3.3V module output voltage | |
J6 | VCCIOA | Out | B32 | PL IO-bank VCCIO |
VCCIOC | Out | B1 | PL IO-bank VCCIO | |
M3.3VOUT | In | C32 | 3.3V module output voltage | |
3.3V | Out | C31 | 3.3V module supply voltage | |
5VIN | In | A1, A2 | Carrier Board supply power |
Table 16: Power Pin description of on-board connector.
Jumper / Header Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J10 | VCCIOA | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - | |
J11 | VCCIOB | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - | |
J12 | VCCIOC | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - |
Table 17: Power Pin description of VCCIO selection jumper pin header.
Main Power Jack and Pins Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J1 | 5VIN | In | - | - |
J6 | 5VIN | In | A1, A2 | '5VIN' power supply to the Carrier Board as alternative to J1 |
J9 | VBAT | In | 1 | Attention: Pin 2 connected to ground. VBAT voltage connected on this pin cause short-circuit. |
Table 18: Main Power jack and pins description.
Peripheral Socket Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J7 / J8 | USB-VBUS | Out | 1 | USB2.0 Type A socket / Micro USB2.0 B socket |
J4 | M3.3VOUT | Out | 4 | MikroSD Card socket VDD |
Table 19: Power pin description of peripheral connector.
XMOD Header Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
JX1 | 3.3V | - | 5 | not connected |
VIO | Out | 6 | connected to 'VCCJTAG' (pin JB2-92) |
Table 20: Power pin description of XMOD/JTAG Connector.
Module Variant | Operating Temperature | USB2.0 Socket | Temperature Range |
---|---|---|---|
TE0706-02 | -40°C to +85°C | USB2.0 Type A socket fitted | Industrial |
TE0706-D-02 | -40°C to +85°C | Micro USB2.0 Type B socket fitted | Industrial |
Table 21: Board variants.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5VIN supply voltage | -0.3 | 7 | V | MP5010A, EN6347QI, EN5311QI data sheet |
Storage temperature | -55 | +85 | °C | Marvell 88E1512 data sheet |
Table 22: Module absolute maximum ratings.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5VIN supply voltage | 4.75 | 5.25 | V | USB2.0 specification concerning 'VBUS' voltage |
Operating temperature | -40 | +85 | °C | - |
Table 23: Module recommended operating conditions.
Industrial grade: -40°C to +85°C.
The TE0706 Carrier Board itself is capable to be operated at industrial grade temperature range.
Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.
Board size: PCB 100mm × 64.5mm. Notice that the USB type A socket on the left and the Ethernet RJ-45 jacks on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106mm. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8mm
PCB thickness: 1.65mm
Highest parts on the PCB are USB type A socket and the Ethernet RJ-45 jacks, approximately 15mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure 6: Board physical dimensions drawing.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2016-06-28 | 01 |
| - | TE0706-01 |
- | 02 |
| - | TE0706-02 |
Table 24: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Figure 7: Board hardware revision number.
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Date | Revision | Contributors | Description |
---|---|---|---|
Ali Naseri |
| ||
2017-07-06 | v.52 | Ali Naseri, Jan Kumann |
|
2017-01-06 | v.1 | Ali Naseri |
|
Table 25: Document change history.