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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

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Overview

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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Key Features

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Excerpt
QSPI SDK Custom Carrier (with other MIO settings as TEBF0808)

Revision History

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Date	Vivado	Project Built	Authors	Description
2017-11-13	2017.2	TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip	John Hartfiel	initial release

Release Notes and Know Issues

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Issues	Description	Workaround	To be fixed version
No known issues	---	---	---

Requirements

Software

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Software	Version	Note
Vivado	2017.2	needed
SDK	2017.2	needed

Hardware

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Additional HW Requirements:

Additional Hardware	Notes

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib	Vivado Project will be generated by TE Scripts
SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

Type	Location	Notes

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

TE0808 Test Board

Design Flow

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_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project
1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
  Note: Select correct one, see TE Board Part Files
  Use Board Part Files, which did not contains with *_tebf0808
Create HDF and export to prebuilt folder
1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
  Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate Programming Files with HSI/SDK
1. Run on Vivado TCL: TE::sw_run_hsi
  Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
  Note: See SDK Projects

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

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Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

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Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

Prepare HW like described on section TE808 Test Board Programming
Connect UART USB (most cases same as JTAG)
Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

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System Design - Vivado

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Block Design

PS Interfaces

Activated interfaces:

Type	Note
DDR
QSPI	MIO
UART0	MIO, please select other one, if you have connected uart to second controller or other MIO

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

Hello TE0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

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No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

Page info

	modified-user
	modified-user

Release 2017.2

All

Page info

	modified-users
	modified-users

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 5

New Version 6

Key

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

QSPI

SD

JTAG

Usage

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

FSBL

Hello TE0808

Additional Software

Appx. A: Change History and Legal Notices

Document Change History

Legal Notices