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# # Common BITGEN related settings for TE0720 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] |
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# set_property BITSTREAM.CONFIG.USR_ACCESSUNUSEDPIN TIMESTAMPPULLUP [current_design] |
Design specific constrain
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# # Constraints for System controller support logic # set_property PACKAGE_PIN K2K16 [get_ports {fclk[0]}PL_pin_K16] set_property IOSTANDARDPACKAGE_PIN LVCMOS18K19 [get_ports {fclk[0]}]PL_pin_K19] set_property CLOCKPACKAGE_DEDICATED_ROUTEPIN FALSEK20 [get_netsports fclk_IBUF[0]] |
Software Design - SDK/HSI
HTML |
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<!--
optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:
Application
FSBL
Xilinx default FSBL
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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optional chapter
Add "No changes." or "Activate: -->List"
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For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
No changes.
Device Tree
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/include/ "system-conf.dtsi"
/ {
};
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Kernel
No changes.
Rootfs
...
PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Software Design - SDK/HSI
HTML |
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<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
Application
FSBL
TE modified 2017.2 FSBL
Functions:
- ReadEEPROM MAC Address and make accessable by UBOOT(need defines on uboot platform-top.h)
- Read CPLD Firmware and SoC Typ
- Confgure Marvell PHY Config
Changes:
- Add te_fsbl_config.h,, te_fsbl_hooks.h te_fsbl_hooks.c, and includ into fsbl_hooks.c
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
HTML |
---|
<!--
optional chapter
Add "No changes." or "Activate: -->List"
--> |
For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
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#include <configs/platform-auto.h>
#define UBOOT_ENV_MAGIC 0xCAFEBABE
#define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00
#define UBOOT_ENV_ADDR 0xFFFFFC04
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Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/* default */
/* Flash */
&qspi {
flash0: flash@0 {
compatible = "w25q256";
};
};
/* ETH PHY */
&gem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
};
};
};
/* USB PHY */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
//compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
iexp@20 { // GPIO in CPLD
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x20>;
gpio-controller;
};
iexp@21 { // GPIO in CPLD
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x21>;
gpio-controller;
};
rtc@6F { // Real Time Clock
compatible = "isl12022";
reg = <0x6F>;
};
};
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Kernel
Activate:
- RTC_DRV_ISL12022
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
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Date | Document Revision | Authors | Description | ||||||||||||||||||||||
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| Work in progress | ||||||||||||||||||||||
2017-10-19 | v.21 | John Hartfiel | Work in progress | ||||||||||||||||||||||
Release 2017.2 | |||||||||||||||||||||||||
2017-11-202017-09-11 | v.1 |
| Initial release | ||||||||||||||||||||||
All |
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