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Overview


Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Key Features


  • Vivado 2018.3
  • PetaLinux
  • SD
  • ETH (use EEPROM MAC)
  • USB
  • I2C
  • RTC
  • VIO PHY LED
  • FSBL for EEPROM MAC and CPLD access
  • Special FSBL for QSPI Programming

Revision History


DateVivadoProject BuiltAuthorsDescription
2019-03-042018.3TE0720-test_board-vivado_2018.3-build_01_20190304100745.zip
TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190304100755.zip
John Hartfiel
  • update for -1CR version only (256MB DDR3)
2019-02-212018.3TE0720-test_board-vivado_2018.3-build_01_20190221125123.zip
TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190221125133.zip
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
2018-08-232018.2

te0720-test_board-vivado_2018.2-build_03_20180823185142.zip
te0720-test_board_noprebuilt-vivado_2018.2-build_03_20180823185158.zip

John Hartfiel
  • DDR setup bugfix for l1if only
2018-08-132018.2te0720-test_board-vivado_2018.2-build_02_20180810162024.zip
te0720-test_board_noprebuilt-vivado_2018.2-build_02_20180810162040.zip
John Hartfiel
  • 2018.2 update
  • Boart Part Files rework
2018-04-262017.4te0720-test_board-vivado_2017.4-build_07_20180426144351.zip
te0720-test_board_noprebuilt-vivado_2017.4-build_07_20180426144405.zip
John Hartfiel
  • new assembly variant
2018-03-122017.4te0720-test_board_noprebuilt-vivado_2017.4-build_06_20180312152408.zip
te0720-test_board-vivado_2017.4-build_06_20180312152419.zip
John Hartfiel
  • add assembly variant
  • script update
2018-01-092017.4te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip
te0720-test_board-vivado_2017.4-build_02_20180109121300.zip
John Hartfiel
  • no design changes
  • set EEPROM MAC with FSBL+u-boot
  • FSBL for QSPI Programming
2017-11-272017.2te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip
te0720-test_board-vivado_2017.2-build_05_20171127153006.zip
John Hartfiel
  • remove duplicated content
2017-11-202017.2te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip
te0720-test_board-vivado_2017.2-build_05_20171122074646.zip
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues


IssuesDescriptionWorkaroundTo be fixed version
Variant with 256MB DDR only(TE0720-03-1CR)wrong netboot offsetrecreate u-boot on petalinux with  reduces netboot offset onlysolved with 2019-03-04 update
Known Issues

Requirements

Software


SoftwareVersionNote
Vivado2018.3needed
SDK2018.3needed
PetaLinux2018.3needed
Software

Hardware


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
 TE0720-03-2IF         2if_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-2IFC3       2if_1gb     REV03|REV02  1GB      32MB       4GB       2.5 mm connectorsNA                
 TE0720-03-2IFC8       2if_1gb     REV03|REV02  1GB      32MB       32GB      NA                NA                 
 TE0720-03-1QF         1qf_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CF         1cf_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CFA        1cf_1gb     REV03|REV02  1GB      32MB       8GB       NA                NA                 
 TE0720-03-2EF         2ef_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CR         1cr_256mb   REV03|REV02  256MB    32MB       NA        NA                NA                 
 TE0720-03-L1IF        l1if_512mb  REV03|REV02  512MB    32MB       4GB       NA                LP DDR3          
 TE0720-03-14S-1C      14s_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1QFA        1qf_1gb     REV03|REV02  1GB      32MB       4GB       NA                Micron Flash     
 TE0720-03-2IFA        2if_1gb     REV03|REV02  1GB      32MB       4GB       NA                Micron Flash     
 TE0720-03-1QFL        1qf_1gb     REV03|REV02  1GB      32MB       4GB       2.5 mm connectorsNA                
Hardware Modules

Design supports following carriers:

Carrier ModelNotes
TE0701
TE0703
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • Used as reference carrier.
TE0705
TE0706
TEBA0841
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support
Hardware Carrier


Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Additional Hardware

Content

For general structure and of the reference design, see Project Delivery

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes
init.sh<design name>/sd/Additional Initialization Script for Linux
Additional design sources

Prebuilt

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.


Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming


Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0720" possible
  4. Copy image.ub on SD-Card
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TE0720 Test Board#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. I2C 1 Bus type: i2cdetect -y -r 1
    3. RTC check: dmesg | grep rtc
    4. ETH0 works with udhcpc
    5. USB: insert USB device
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager 

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder

  • Monitoring: PHY LED

Vivado Hardware Manager

System Design - Vivado


Block Design

Block Design


PS Interfaces

TypeNote
DDR---
QSPIMIO
ETH0MIO
USB0MIO
SD0MIO
SD1MIO
UART0MIO
UART1MIO
I2C0MIO
I2C1EMIO
GPIOMIO
TTC0..1EMIO
WDTEMIO

Constrains

Basic module constrains

_i_bitgen_common.xdc
#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design
_i_common.xdc
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

_i_TE0720-SC.xdc
#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design - SDK/HSI


For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY
    • USB PHY Reset
    • Configure LED usage

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


hello_te0720

Hello World App in Endless loop.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux


For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
  • CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
  • CONFIG_SUBSYSTEM_NETBOOT_OFFSET=0x8000000  ! Must be done manually for 256MB DDR only → not done on with HDF import from the template!

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y
  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"


/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQ_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
#define CONFIG_SYS_I2C_EEPROM_ADDR             0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
#define CONFIG_SYS_EEPROM_SIZE                 1024 /* Bytes */
#define CONFIG_SYS_I2C_MUX_ADDR                0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_SEL          0x4
#endif

#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"



Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* default */

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};

/* USB PHY */

/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {

    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
        gpio-controller;
    };

    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
        gpio-controller;
    };

    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed.


Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • Some FSBL notes
  • wrong link
2019-03-06v.28John Hartfiel
  • Fixed prebuilt issue for TE0720-03-1CR
2019-03-01v.27John Hartfiel
  • Known issue for TE0720-03-1CR linux design

2019-02-21

v.26John Hartfiel
  • 2018.3 release finished (include design reworks)
2018-08-30v.25John Hartfiel
  • update documentation PS configuration

2018-08-23

v.24

John Hartfiel
  • update l1if boart parts

2018-08-13

v.23John Hartfiel
  • 2018.4 release

2018-04-26

v.22John Hartfiel
  • add assembly variant
2018-02-20v.20John Hartfiel
  • small documentation update
2018-01-09v.16John Hartfiel
  • Release 2017.4
  • Documentation update
2017-11-27v.14John Hartfiel
  • Typo correction
  • Design Files update
2017-11-22v.12John Hartfiel
  • Update HW list
2017-11-22

v.11

John Hartfiel
  • Release 2017.2
2017-11-20v.1
  • Initial release
--All--
Document change history.

Legal Notices

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WEEE

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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