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Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2
  • PetaLinux
  • SD
  • ETH (use EEPROM MAC)
  • USB
  • I2C
  • RTC
  • FSBL for EEPROM MAC and CPLD access / petalinux patch
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
John Hartfiel
  • bugfix missing binaries+ boot.scr file(supports now QSPI and SD boot with image.ub on SD)
John Hartfiel
  • 2020.2 update
  • add boot.scr file
  • petalinuxx fsbl patch (betaversion)
John Hartfiel
  • script update
John Hartfiel
  • script update for linux user
John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
John Hartfiel
  • 2019.2 update
  • Vitis support
John Hartfiel
  • update for -1CR version only (256MB DDR3)
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features

John Hartfiel
  • DDR setup bugfix for l1if only
John Hartfiel
  • 2018.2 update
  • Boart Part Files rework
John Hartfiel
  • new assembly variant
John Hartfiel
  • add assembly variant
  • script update
John Hartfiel
  • no design changes
  • set EEPROM MAC with FSBL+u-boot
  • FSBL for QSPI Programming
John Hartfiel
  • remove duplicated content
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version

Linux binaries are missing
boot.scr are only prepared for SD Boot
create and modifiy by your self or use 2019.2 designsolved with 2020-04-01 update
Variant with 256MB DDR only(TE0720-03-1CR)wrong netboot offsetrecreate u-boot on petalinux with  reduces netboot offset onlysolved with 2019-03-04 update
Known Issues




needed, Vivado is included into Vitis installation



Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
 TE0720-03-2IF         2if_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-2IFC3       2if_1gb     REV03|REV02  1GB      32MB       4GB       2.5 mm connectorsNA                
 TE0720-03-2IFC8       2if_1gb     REV03|REV02  1GB      32MB       32GB      NA                NA                 
 TE0720-03-1QF         1qf_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CF         1cf_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CFA        1cf_1gb     REV03|REV02  1GB      32MB       8GB       NA                NA                 
 TE0720-03-2EF         2ef_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1CR         1cr_256mb   REV03|REV02  256MB    32MB       NA        NA                NA                 
 TE0720-03-L1IF        l1if_512mb  REV03|REV02  512MB    32MB       4GB       NA                LP DDR3          
 TE0720-03-14S-1C      14s_1gb     REV03|REV02  1GB      32MB       4GB       NA                NA                 
 TE0720-03-1QFA        1qf_1gb     REV03|REV02  1GB      32MB       4GB       NA                Micron Flash     
 TE0720-03-2IFA        2if_1gb     REV03|REV02  1GB      32MB       4GB       NA                Micron Flash     
 TE0720-03-1QFL        1qf_1gb     REV03|REV02  1GB      32MB       4GB       2.5 mm connectorsNA                
Hardware Modules

Design supports following carriers:

Carrier ModelNotes
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • Used as reference carrier.
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes<design name>/sd/Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Source*.scr

Distro Boot file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis  and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/ and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see also TE Board Part Files
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf, boot.src and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size>" of the selected device
  8. Generate Programming Files with Vitis
    • Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis
    • (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated


Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0720" possible
  4. Copy image.ub on SD-Card
    1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card


  1. Copy image.ub, boot.scr  and Boot.bin on SD-Card.
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section TE0720 Test Board#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR


  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. I2C 1 Bus type: i2cdetect -y -r 1
    3. RTC check: dmesg | grep rtc
    4. ETH0 works with udhcpc
    5. USB: insert USB device
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. scripts
      1. add script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager 

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder

  • Monitoring: PHY LED

Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design

PS Interfaces



Basic module constrains

# Common BITGEN related settings for TE0720 SoM
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

# Constraints for System controller support logic
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design - Vitis

For SDK project creation, follow instructions from:



Template location: ./sw_lib/sw_apps/


TE modified 2020.2 FSBL


  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY
    • USB PHY Reset
    • Configure LED usage


TE modified 2020.2 FSBL


  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello World App in Endless loop.


U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description



Note: for variants with 256MB DDR only , change NET Boot Address to 0x8000000  on boot.src file


Start with petalinux-config -c u-boot


  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

#include <configs/zynq-common.h>
#include <configs/platform-auto.h>

#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"

Device Tree

/include/ "system-conf.dtsi"
/ {

/* default */
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
/* USB PHY */
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;

FSBL patch

Must be add manually, see template


Start with petalinux-config -c kernel




Start with petalinux-config -c rootfs


  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)


See: \os\petalinux\project-spec\meta-user\recipes-apps\


Script App to load from SD Card if available.


Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • Design update
2021-02-26v.41John Hartfiel
  • add issue notes
2021-02-17v.40John Hartfiel
  • 2020.2 release
2020-03-25v.39John Hartfiel
  • script update
2020-01-22v.38John Hartfiel
  • script update for linux user
2020-01-14v.37John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-19v.36John Hartfiel
  • 2019.2 release
2019-12-03v.34John Hartfiel
  • bugfix document link
2019-10-28v.33John Hartfiel
  • removed remove instructions that are no longer used


v.31John Hartfiel
  • Some FSBL notes
  • wrong link
2019-03-06v.28John Hartfiel
  • Fixed prebuilt issue for TE0720-03-1CR
2019-03-01v.27John Hartfiel
  • Known issue for TE0720-03-1CR linux design


v.26John Hartfiel
  • 2018.3 release finished (include design reworks)
2018-08-30v.25John Hartfiel
  • update documentation PS configuration



John Hartfiel
  • update l1if boart parts


v.23John Hartfiel
  • 2018.4 release


v.22John Hartfiel
  • add assembly variant
2018-02-20v.20John Hartfiel
  • small documentation update
2018-01-09v.16John Hartfiel
  • Release 2017.4
  • Documentation update
2017-11-27v.14John Hartfiel
  • Typo correction
  • Design Files update
2017-11-22v.12John Hartfiel
  • Update HW list


John Hartfiel
  • Release 2017.2
  • Initial release
Document change history.

Legal Notices

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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