Page History

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Key Features

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Revision History

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Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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• TE0??? "Test Board" Reference Design Download Area

Design Flow

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1. Generate Platform Project or use prebuilt from download
2. ...

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

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Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

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SD

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section 46040440 Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root

System Design - Vivado

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Block Design

PS Interfaces

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};

Kernel

No changes.

Rootfs

No changes.

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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No additional software is needed.

SDSoC Design

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Description currently not available.

SDSoC Platform

SDSoC Demo Examples

SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples

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• <xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
• <xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
• <xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv

Array partition

This example shows how to use array partitioning to improve performance of a hardware function.

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•  #pragma HLS ARRAY_PARTITION
•  complete

Burst rw

This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.

Key Concepts:

•  Burst Access

Custom data type

This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.

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Keywords:

•  struct
•  packed
•  aligned

Data access random

This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.

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•  #pragma HLS PIPELINE
•  #pragma SDS access_pattern(a:RANDOM, b:RANDOM)
•  #pragma SDS data copy

Dependence inter

This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.

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Keywords:

•  DEPENDENCE
•  inter

Direct connect

This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.

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•  #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)

Dma sg

This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.

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•  #pragma SDS access_parttern(a:SEQUENTIAL)
•  #pragma SDS data_mover(a:AXIDMA_SG)
•  #pragma SDS data copy

Dma simple

This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.

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• #pragma SDS access_parttern(a:SEQUENTIAL)
• #pragma SDS data_mover(a:AXIDMA_SIMPLE)
• #pragma SDS data copy

Full array 2d

This is a simple example of accessing full data from 2D array.

Key Concepts:

•  2D data array access

Hello vadd

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This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.

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Keywords:

•  - #pragma HLS PIPELINE

Lmem 2rw

This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.

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•  #pragma HLS UNROLL FACTOR=2

Loop fusion

This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.

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Keywords:

•  #pragma HLS PIPELINE

Loop perfect

This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.

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• #pragma HLS PIPELINE
• #pragma HLS ARRAY_PARTITION

Loop pipeline

This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.

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Keywords:

• #pragma HLS PIPELINE

Loop reorder

This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.

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•  #pragma HLS PIPELINE
•  #pragma HLS ARRAY_PARTITION

Row array 2d

This is a simple example of accessing each row of data from 2D array.

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• Row of 2D data array access

Keywords:

• hls::stream

Shift register

This example demonstrates how to shift values in each clock cycle.

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• #pragma HLS ARRAY_PARTITION

Systolic array

This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.

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• #pragma HLS PIPELINE
• #pragma HLS ARRAY_PARTITION

Sys port

This is a simple example which demonstrates sys_port usage.

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• #pragma SDS data sys_port
• #pragms HLS PIPELINE
• sds_alloc_non_cacheable

Wide memory rw

This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.

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• wide memory access
• burst read and write
• custom datatype

Keywords:

• struct

Window array 2d

This is a simple example of accessing window of data from 2D array.

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• #pragma HLS DATAFLOW
• #pragma HLS PIPELINE
• #pragma HLS stream

File IO Video Processing

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.

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The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Dense Optical Flow

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.

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The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Stereo Block Matching

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.

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The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Legal Notices

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