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TEF1001 SI5338 Configuration, DDR Configuration and PCIe Core Example Design.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • MicroBlaze
  • I2C
  • Flash
  • FMeter
  • PCIe
  • SI5338
  • DDR3 ECC SODIMM (currently ECC disabled)

Revision History

DateVivadoProject BuiltAuthorsDescription
John Hartfiel
  • Add -410 assembly variant
  • Add some notes on Board part Files (summary window description)
John Hartfiel
  • 2018.2
  • add TEF1001-02
  • MIG Configuration for AW12P7218BLK0M (4GB for REV01)
  • MIG Configuration for AW24P7228BLK0M (8GB for REV02)
  • BUGFIX QSPI IP configuration
  • add SREC to load application into DDR
John Hartfiel
  • 2017.4 update
  • new assembly variant
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
DDR3 ECC SODIMMDDR3 does not work with ECC enabled

Disable ECC:

  • for Block Design MIG with AXI Interface, create 64Bit MIG
  • for RTL MIG with Native Interface, disable ECC on MIG configuration and use 72Bit for Data
Known Issues



SI5338 Clock Builder---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TEF1001-01-160-2I1_160_2REV01DDR3 ECC SODIMM*32MB
  • DDR configured for AW12P7218BLK0M (4GB for REV01)
TEF1001-01-325-2C1_325_2REV01DDR3 ECC SODIMM*32MB
  • DDR configured for AW12P7218BLK0M (4GB for REV01)
TEF1001-02-160-2I2_160_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)
TEF1001-02-325-2C2_325_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)
TEF1001-02-410-2I2_410_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)

* PCB REV01 DDR3 ECC SODIMM is limited to 4GB, for PCB REV02 up to 8GB is possible

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
PC with PCIe Card slot
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
 JTAG Programmer
  •  TE0790 with TE0791 for CPLD or FPGA
  • Xilinx compatible JTAG programmer for FPGA
DDR3 (204 Pin with ECC)
  • for example:
    • AW12P7218BLK0M ( max. 4GB for REV01)
    • AW24P7228BLK0M (max. 8GB for REV02)
Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
Design sources

Additional Sources

SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration
Additional design sources





BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File



Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)



File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems



Converted Software Application for MicroBlaze Processor Systems

Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/ and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
      (optional) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
      Note: See SDK Projects
    2. (optional )Copy "prebuilt\software\<short dir>\srec_spi_bootloader.elf" into "\firmware\microblaze_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging


  1. Connect JTAG and Power ON PC
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_mcsfile -swapp hello_tef1001
  4. Reboot PC


Not supported.


  • Connect Vivado HW Manager and program FPGA
    Note: PCIe enumeration will be not done in this case. SREC Bootloader need Hello TEF1001 application on QSPI Flash for output


  1. Prepare HW like described on section Programming
  2. Power On PCB
    Note: 1. FPGA Load Bitfile  into FPGA, modified SREC Bootloader configure SI5338 and load application from QSPI into DDR (Depends on linker script)

JTAG/UART Console:

  • Launch the XSDB console on SDK (Xilinx → XSCT Console):
    • type: connect
    • type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
    • type: jtagterminal -start
    • Separat console starts:

Vivado HW Manager:

  1. Open Vivado HW Manager
  2. Add VIO to Dashboard:
  3. Set Radix to unsigned integer for FMeterCLKs (labt_SI_*)
  4. Control:
    1. USER LEDs are selectable
      Note USR_CPLD_LED on PCB REV1 and REV02, USR_LED Matrix only on REV02
    2. Optional PCIe Core Reset (on FPGA only)
    3. Optional System Reset (on FPGA only)
  5. Read: All SI5338 CLKs (Unit Hz), PCIe Cor MMCM Lock signal, MIG MMCM Lock signal, MIG Init Calibration Done


  • Use for example PCI-Z (Win) or KInfoCenter (Linux) or lspci command (Linux console) to detect PCIe Card

System Design - Vivado

Block Design

Block Design


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

#USER LED Matrix

set_property PACKAGE_PIN K25 [get_ports {USR_LED[0]}]
set_property PACKAGE_PIN K26 [get_ports {USR_LED[1]}]
set_property PACKAGE_PIN P26 [get_ports {USR_LED[2]}]
set_property PACKAGE_PIN R26 [get_ports {USR_LED[3]}]
set_property PACKAGE_PIN N16 [get_ports {USR_LED[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[4]}]

set_property PACKAGE_PIN J26 [get_ports {USR_LED[5]}]
set_property PACKAGE_PIN H26 [get_ports {USR_LED[6]}]
set_property PACKAGE_PIN E26 [get_ports {USR_LED[7]}]
set_property PACKAGE_PIN A24 [get_ports {USR_LED[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[8]}]

set_property PACKAGE_PIN F19 [get_ports {USR_LED[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[9]}]

# FEX11
set_property PACKAGE_PIN B21 [get_ports {USR_CPLD_LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_CPLD_LED[0]}]
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
##set_property PACKAGE_PIN AB11 [get_ports CLK_DDR3_200MHz_clk_p]
##set_property PACKAGE_PIN AC11 [get_ports CLK_DDR3_200MHz_clk_n]
##set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
##set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]
set_property PACKAGE_PIN C23 [get_ports {spi_rtl_ss_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {spi_rtl_ss_io[0]}]
set_property PACKAGE_PIN B24 [get_ports spi_rtl_io0_io]
set_property PACKAGE_PIN A25 [get_ports spi_rtl_io1_io]
set_property PACKAGE_PIN B22 [get_ports spi_rtl_io2_io]
set_property PACKAGE_PIN A22 [get_ports spi_rtl_io3_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io0_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io1_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io2_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io3_io]
set_property PACKAGE_PIN G26 [get_ports SCF_cpld_1_scl]
set_property PACKAGE_PIN F25 [get_ports SCF_cpld_14_oe]
set_property PACKAGE_PIN G25 [get_ports SCF_cpld_16_sda]
set_property IOSTANDARD LVCMOS18 [get_ports SCF_cpld_1_scl]
set_property IOSTANDARD LVCMOS18 [get_ports SCF_cpld_14_oe]
set_property IOSTANDARD LVCMOS18 [get_ports SCF_cpld_16_sda]
#SI5338 CLKs
set_property PACKAGE_PIN H6 [get_ports {SI_MGT115_0_clk_p[0]}]

set_property PACKAGE_PIN G22 [get_ports {SI_FCLK_clk_p[1]}]
set_property PACKAGE_PIN D23 [get_ports {SI_FCLK_clk_p[2]}]
set_property PACKAGE_PIN G24 [get_ports {SI_FCLK_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {SI_FCLK_*}]
# FEX0
set_property PACKAGE_PIN B20 [get_ports {PCI_PERSTN}]
set_property IOSTANDARD LVCMOS18 [get_ports {PCI_PERSTN}]
set_property PACKAGE_PIN K6 [get_ports {CLK_PCIe_100MHz_clk_p[0]}]
set_property PACKAGE_PIN N4 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN R4 [get_ports {pcie_7x_mgt_rxp[3]}]
set_property PACKAGE_PIN L4 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN J4 [get_ports {pcie_7x_mgt_rxp[0]}]


#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN AC9 [get_ports CLK_DDR3_200MHz_clk_p]
set_property PACKAGE_PIN AD9 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]


#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN AB11 [get_ports CLK_DDR3_200MHz_clk_p]
set_property PACKAGE_PIN AC11 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects


Template location: ./sw_lib/sw_apps/


  • Xiline Hello World as endless loop


  • Si5338 I2C Configuration example only.


  • modified Xilinx SREC Bootloader, including SI5338 configuration
    • modified Files: blconfig.h, bootloader.c

    • add Files: si5338.h, si5338.c, register_map.h

    • modified  xilisf_v5_11: xilisf.mld (default Flash Typ:5)

Additional Software


File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision



  • typo correction part name
  • typo correction on programming chapter
  • note pcie

v.9John Hartfiel
  • add -410 assembly variant

v.8John Hartfiel
  • 2018.2 release

v.6John Hartfiel
  • 2017.4 release
2018-02-08v.5John Hartfiel
  • 2017.2 release
2017-11-28v.1John Hartfiel
  • initial release
Document change history.

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