Page History
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- Xilinx Artix-7 FPGA (15T to 200T) supported by the free Xilinx Vivado WebPACK software
- Both industrial and commercial temperature ranges available
- Rugged for high shock resistance and high vibration
- 1 GByte DDR3 32-bit SDRAM
- 10/100 Mbit Ethernet PHY
- MAC address EEPROM
- 32 MByte QSPI Flash memory (with XiP support)
- Programmable clock generator
- Transceiver clock (default 125 MHz)
- Fabric clock (default 200 MHz)
- Transceiver clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 158 FPGA I/Os (78 differential pairs) available via board-to-board connectors (quantity depends on assembly variant)
- 4 GTP (high-performance transceiver) lanes
- GTP (high-performance transceiver) clock input
- On-board high-efficiency DC-DC converters
- 12A x 1.0V power rail
- 1.5A x 1.8V power rail
- 1.5A x 1.5V power rail
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- User configurable LEDs
- Evenly-spread supply pins for good signal integrity
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| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|---|---|---|---|
| 13 | JM1 | 10 | VCCIO13 | Supplied by the baseboard. Not connected available on XC7A35T assembly variant. |
| 13 | JM3 | 20 | VCCIO13 | Supplied by the baseboard. Not connected available on XC7A35T assembly variant. |
| 14 | JM1 | 8 | 3.3V | |
| 14 | JM2 | 18 | 3.3V | |
| 14 | JM3 | 4 | 3.3V | |
| 15 | JM2 | 48 | VCCIO15 | Supplied by the baseboard. |
| 15 | JM2 | 2 | VCCIO15 | Supplied by the baseboard. |
| 16 | JM1 | 48 | VCCIO16 | Supplied by the baseboard. |
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