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Revision History
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Date | Vivado | Project Built | Authors | Description |
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2018.01.09 | 2017.4 | John Hartfiel |
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2017-11-27 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip te0720-test_board-vivado_2017.2-build_05_20171127153006.zip | John Hartfiel |
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2017-11-20 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip | John Hartfiel |
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Software | Version | Note |
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Vivado | 2017.24 | needed |
SDK | 2017.24 | needed |
PetaLinux | 2017.24 | needed |
Hardware
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes | ||
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te0720-03-2if | 2if | REV02REV02, REV03 | 1GB | 32 | ||||
te0720-03-2ifc3 | 2if | REV02REV02, REV03 | 1GB | 32 | 2.5 mm connector | |||
te0720-03-2ifc8 | 2if | REV02REV02, REV03 | 1GB | 32 | 32GB eMMC |
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te0720-03-1qf | 1qf | REV02REV02, REV03 | 1GB | 32 | ||||
te0720-03-1cf | 1cf | REV02REV02, REV03 | 1GB | 32 | ||||
te0720-03-2ef1cfa2ef | 1cf | REV02REV02, REV03 | 1GB | 32 | 8GB eMMC | |||
te0720-03-1cr2ef | 2ef | REV02, REV03 | 1GB | 32 | ||||
te0720-03-1cr | 1cr | REV02 | 1cr | REV02, REV03 | 256MB | 32 | ||
te0720-03-l1if | l1if | REV02REV02, REV03 | 512MB (L) | 32 | ||||
te0720-03-14s-1c | 14s | REV02REV02, REV03 | 1GB (L) | 32 |
Design supports following carriers:
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Reference Design is available on:
Design Flow
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The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup - Copy image.ub on SD-Card
- Insert SD-Card
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Example:
Connect JTAG and power on PCB
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Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
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- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
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Application
FSBL
TE modified 2017.2 4 FSBL
Functions:
- Read EEPROM MAC Address and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- Read CPLD Firmware and SoC Type
- CPLD Interface
- Configure Marvell PHY
Changes:
- Add te_fsbl_config.h,, te_fsbl_hooks.h te_fsbl_hooks.c, and includ into fsbl_hooks.c_hooks.c, and includ into fsbl_hooks.c
zynq_fsbl_flash
TE modified 2017.4 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Hello TE0720
Hello World App in Endless loop.
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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#include <configs/platform-auto.h> #define UBOOT_ENV_MAGIC 0xCAFEBABE #define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00 #define UBOOT_ENV_ADDR 0xFFFFFC04 h> #define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp" |
Device Tree
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/include/ "system-conf.dtsi" / { }; /* default */ /* Flash */ &qspi { flash0: flash@0 { compatible = "w25q256"; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x20>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
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2017-11-27 | v.14 | John Hartfiel |
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2017-11-22 | v.12 | John Hartfiel |
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2017-11-22 | v.11 | John Hartfiel |
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2017-11-20 | v.1 |
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