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Excerpt
  • QSPI
  • SDK
  • Custom Carrier (
with other MIO settings as TEBF0808)
  • minimum PS Design with available module components only)
  • Special FSBL for QSPI Programming


Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-01-182017.4
John Hartfiel
  • rework Board Part Files
2017-11-162017.2TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip
TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip
John Hartfiel
  • Update Board Part CSV File with new Flash assembly variants

2017-11-14

2017.2TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip
TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip
John Hartfiel
  • Initial release

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SoftwareVersionNote
Vivado2017.24needed
SDK2017.24needed

Hardware

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Hardware Support
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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0803-ES1 es1es1REV012GB64
 
TE0803-01-02EG-1E 2eg2egREV01 TE0808-2ES2 2es22GB64REV01
 
TE0803-01-02CG-1E / *EA2cgREV012GB64/  different QSPI Flash size

TE0803-01-03EG-1E / *EA3egREV012GB64/  different QSPI Flash size

TE0803-01-03CG-1E / *EA3cgREV01/  different QSPI Flash size

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design. * Only different Flash size.

Design supports following carriers:

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2GB64

TE0803-01-02EG-1EA2egREV012GB128

TE0803-01-02CG-1EA2cgREV012GB128

TE0803-01-03EG-1EA3egREV012GB128

TE0803-01-03CG-1EA3cgREV012GB128

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design. * Only different Flash size.

Design supports following carriers:

Carrier ModelNotes
Custom PCB use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808Used as reference carrier.
TEBT0808Change UART0 to UART1 (MIO68...69) and regenerate design

Additional HW Requirements:

Additional HardwareNotes

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For general structure and of the reference design, see Project Delivery

Design Sources

TypeLocation

Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

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Reference Design is available on:

Design Flow

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  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which did not contains ends with *_tebf0808
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

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  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
  4. Select JTAG as Boot Mode (see Carrier Description and ZynqMP TRM)
  5. Connect JTAG to Host PC
  6. Power On
  7. Open Vivado Hardware Manager with Auto Connect
  8. Right Click to FPGA Device XCU... and select Add Configuration Memory Device
    1. Select correct Flash Typ (see schematics or FPGAFLASHTYP on test_board/board_files/TE0808_board_files.csv)
  9. Open Program Configuration Memory Device
  10. Configuration file: test_board/prebuilt/boot_image/<short dir>/hello_te0803/Boot.bin
  11. Zynq FSBL: test_board/prebuilt/software/<short dir>/zynqmp_fsbl.elf
  12. Program Device Flash

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP


SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

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TypeNote
DDR
QSPIMIO
UART0MIO, please select other one, if you have connected uart to second controller or other MIO
SWDT0..1
TTC0..3

Constrains

Basic module constrains

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For SDK project creation, follow instructions from:

SDK Projects

Application

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zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

Hello TE0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

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DateDocument RevisionAuthorsDescription

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  • Release 2017.4 (working in process)
2017-11-16v.4John Hartfiel
  • Update assembly versions with new Flash size
2017-11-14v.3John Hartfiel
  • Release 2017.2
 All

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