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Overview


Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2

  • QSPI

  • Custom Carrier (minimum PS Design with available module components only)

  • Modified FSBL (some additional outputs only)

  • Special FSBL for QSPI Programming

Revision History

Date

Vivado

Project Built

Authors

Description

2021-09-062020.2TE0803-test_board-vivado_2020.2-build_7_20210906104518.zip
TE0803-test_board_noprebuilt-vivado_2020.2-build_7_20210906104536.zip
Manuela Strücker
  • 2020.2 update
  • update document style

2020-04-06

2019.2

TE0803-test_board-vivado_2019.2-build_9_20200406081019.zip

TE0803-test_board_noprebuilt-vivado_2019.2-build_9_20200406081036.zip

John Hartfiel

  • new assembly variants

2020-03-25

2019.2

TE0803-test_board-vivado_2019.2-build_8_20200325082253.zip

TE0803-test_board_noprebuilt-vivado_2019.2-build_8_20200325082311.zip

John Hartfiel

  • script update

2020-01-23

2019-2

TE0803-test_board-vivado_2019.2-build_3_20200123070036.zip

TE0803-test_board_noprebuilt-vivado_2019.2-build_3_20200123070049.zip

John Hartfiel

  • 2019.2 update

  • Vitis support

  • FSBL SI programming procedure update 

2019-5-06

2018.3

TE0803-test_board_noprebuilt-vivado_2018.3-build_05_20190506161948.zip

TE0803-test_board-vivado_2018.3-build_05_20190506161936.zip

John Hartfiel

  • custom FSBL

  • new assembly variants

2018-10-26

2018.2

TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip

TE0803-test_board-vivado_2018.2-build_03_20181026141651.zip

John Hartfiel

  • new assembly variant

2018-08-14

2018.2

TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip

TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip

John Hartfiel

  • new assembly variant

2018-07-13

2018.2

TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip

TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip

John Hartfiel

  • additional notes for FSBL generated with Win SDK

  • changed *.bif

2018-05-17

2017.4

TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip

TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip

John Hartfiel

  • new assembly variant

2018-04-11

2017.4

TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip

TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip

John Hartfiel

  • bugfix TE0803-01-04EG board part file

2018-02-13

2017.4

TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip

TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip

John Hartfiel

  • new assembly variant

2018-02-05

2017.4

TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip

TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip

John Hartfiel

  • new assembly variant

2018-01-31

2017.4

TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip

TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip

John Hartfiel

  • new assembly variant

2018-01-18

2017.4

TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip

TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip

John Hartfiel

  • rework Board Part Files

2017-11-16

2017.2

TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip

TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip

John Hartfiel

  • Update Board Part CSV File with new Flash assembly variants

2017-11-14

2017.2

TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip

TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip

John Hartfiel

  • Initial release

Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashProgramming QSPI flash fails sometimesuse Vivado 2019.2 for programming
Known Issues

Requirements

Software

SoftwareVersionNote
Vitis2020.2needed, Vivado is included into Vitis installation
Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0803-01-02EG-1E2eg_2gbREV012GB64MBNANANA
TE0803-01-02CG-1E2cg_2gbREV012GB64MBNANANA
TE0803-01-03EG-1E3eg_2gbREV012GB64MBNANANA
TE0803-01-03CG-1E3cg_2gbREV012GB64MBNANANA
TE0803-01-02EG-1EA2eg_2gbREV012GB128MBNANANA
TE0803-01-02CG-1EA2cg_2gbREV012GB128MBNANANA
TE0803-01-03EG-1EA3eg_2gbREV012GB128MBNANANA
TE0803-01-03CG-1EA3cg_2gbREV012GB128MBNANANA
TE0803-02-03EG-1EB3eg_4gbREV02|REV014GB128MBNANANA
TE0803-01-04CG-1EA4cg_2gbREV012GB128MBNANANA
TE0803-02-04EV-1EA4ev_2gbREV02|REV012GB128MBNANANA
TE0803-01-04EV-1E34ev_2gbREV012GB128MBNA1 mm connectorsNA
TE0803-01-04EG-1EA4eg_2gbREV012GB128MBNANANA
TE0803-01-04CG-1EB4cg_2gbREV012GB256MBNANANA
TE0803-01-05EV-1EA5ev_2gbREV012GB128MBNANANA
TE0803-01-05EV-1IA5ev_i_2gbREV012GB128MBNANANA
TE0803-02-04EV-1E34ev_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-02-04EG-1E34eg_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-03-2AE11-A2cg_2gbREV032GB128MBNANANA
TE0803-03-2BE11-A2eg_2gbREV032GB128MBNANANA
TE0803-03-3AE11-A3cg_2gbREV032GB128MBNANANA
TE0803-03-3BE11-A3eg_2gbREV032GB128MBNANANA
TE0803-03-4AE11-A4cg_2gbREV032GB128MBNANANA
TE0803-03-4BE11-A4eg_2gbREV032GB128MBNANANA
TE0803-03-4BE21-L4eg_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4BI21-A4eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DE11-A4ev_2gbREV032GB128MBNANANA
TE0803-03-4DE21-L4ev_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GE21-L4eg_2_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-5DE11-A5ev_2gbREV032GB128MBNANANA
TE0803-03-5DI21-A5ev_i_4gbREV034GB128MBNANANA
TE0803-03-3RI21-A3eg_li_4gbREV034GB128MBNANANA
TE0803-03-3BI21-A3eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DI21-L4ev_i_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GI11-A4eg_2i_2gbREV032GB128MBNANANA
TE0803-03-4GE11-A4eg_2_2gbREV032GB128MBNANANA
TE0803-03-4GI21-A4eg_2i_4gbREV034GB128MBNANANA
TE0803-03-5BE11-A5eg_2gbREV032GB128MBNANANA
TE0803-03-5DI24-A5ev_i_4gbREV034GB512MBNANANA
TE0803-03-4BI21-X4eg_i_4gbREV034GB128MBNANAU41 replaced with diode
TE0803-03-3BE21-A3eg_4gbREV034GB128MBNANANA
TE0803-03-3BE31-A*3eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-2AE11-A2cg_2gbREV042GB128MBNANANA
TE0803-04-2BE11-A2eg_2gbREV042GB128MBNANANA
TE0803-04-3AE11-A3cg_2gbREV042GB128MBNANANA
TE0803-04-3BE11-A3eg_2gbREV042GB128MBNANANA
TE0803-04-4BE21-L4eg_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4BI21-A4eg_i_4gbREV044GB128MBNANANA
TE0803-04-4BI21-X4eg_i_4gbREV044GB128MBNANAU41 replaced with diode
TE0803-03-4BI61-A4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-03-4BI61-X4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-4BI61-A4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4BI61-X4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4DE11-A4ev_2gbREV042GB128MBNANANA
TE0803-04-4DE21-L4ev_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4DI21-L4ev_i_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-03-4DI21-D4ev_i_4gbREV034GB128MBNA
NA
TE0803-04-4DI21-D4ev_i_4gbREV044GB128MBNA
NA
TE0803-04-4GE21-L4eg_2_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4GI21-A4eg_2i_4gbREV044GB128MBNANANA
TE0803-04-5BE11-A5eg_2gbREV042GB128MBNANANA
TE0803-04-5DE11-A5ev_2gbREV042GB128MBNANANA
TE0803-04-5DI21-A5ev_i_4gbREV044GB128MBNANANA

*used as reference

Hardware Modules
Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this board part files are not used for this reference design.

Design supports following carriers:

Carrier Model

Notes

Custom PCB

use simple Board Part files, if MIO connected is different to TEBF0808

TEBF0808*

Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

TEBT0808-01

Change UART0 to UART1 (MIO68...69) and regenerate design

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional Hardware

Notes

---

---

*used as reference

Additional Hardware

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
Design sources

Additional Sources

Type

Location

Notes

---

---

---

Additional design sources

Prebuilt


File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

Diverse Reports

---

Report files in different formats

Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

Prebuilt files (only on ZIP with prebult content)

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")


  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    _create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"

  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

      Important: Use Board Part Files, which did not ends with *_tebf0808

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch


Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0803

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


SD-Boot mode

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with Vitis Debugger into device

Usage

QSPI Boot:

  1. Prepare HW like described on section Programming

  2. Connect UART USB (most cases same as JTAG)

  3. Select QSPI as Boot Mode

    Note: See TRM of the Carrier, which is used.

  4. Power On PCB

    1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,

System Design - Vivado


Block Design

Block Design


PS Interfaces

Activated interfaces:

Type

Note

DDR


QSPI

MIO

UART0

MIO, please select other one, if you have connected UART to second controller or other MIO

SWDT0..1


TTC0..3


PS Interfaces

Constrains

Basic module constrains

_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - Vitis


For Vitis project creation, follow instructions from:

Vitis


Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software


No additional software is needed.

Appx. A: Change History and Legal Notices


Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.


Date

Document Revision

Authors

Description

v.25

Manuela Strücker

  • Release 2020.2

2020-04-06v.24John Hartfiel
  • new assembly variants

2020-03-25

v.23

John Hartfiel

  • Script update

2020-01-23

v.22

John Hartfiel

  • Release 2019.2

2019-05-07

v.21

John Hartfiel

  • Release 2018.3

2018-10-26

v.18

John Hartfiel

  • new assembly variant

2018-08-14

v.16

John Hartfiel

  • new assembly variant

2018-07-13

v.15

John Hartfiel

  • Release 2018.2

2018-05-18

v.14

John Hartfiel

  • new assembly variant

2018-04-11

v.13

John Hartfiel

  • bugfix board part file

2018-04-03

v.11

John Hartfiel

  • new assembly variant

2018-01-18

v.6

John Hartfiel

  • Release 2017.4

2017-11-16

v.4

John Hartfiel

  • Update assembly versions with new Flash size

2017-11-14

v.3

John Hartfiel

  • Release 2017.2


All


Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.





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