Page History

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17

Date	Vivado	Project Built	Authors	Description
2018-01-	18	2017.4	TE0808-StarterKit-vivado_2017.4-build_05_20180117094213.zipTE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180117094231.zip		John Hartfiel	bugfix USB small board part update
2018-01-15	2017.4	TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip TE0808-StarterKit_noprebuilt-vivado_2017.4-build_03_20180115092511.zip	John Hartfiel	rework board part files rework design
2017-12-18	2017.2	TE0808-StarterKit_noprebuilt-vivado_2017.2-build_07_20171219151749.zip TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip	John Hartfiel	initial release

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initial release

Release Notes and Know Issues

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Issues	Description	Workaround/Solution	To be fixed version
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Requirements

Software

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Requirements

Software

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Design supports following modules:

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others	Notes

TE0808

TE0803-ES1

es1

es1_sk

REV02, REV03

REV01

2GB

64

64MB

TE0808-ES2 es2

TE0803-01-02EG-1E

2eg_sk

REV03, REV04

REV01

2GB

64

64MBTE0808-2ES2 2es2


TE0803-01-02CG-1E	2cg_sk

REV03, REV04

REV01

2GB

64MB

64

TE0808


TE0803-

04

01-

09EG

03EG-

1EA

1E

9eg

3eg_

1ea_

sk

REV04

REV01

2GB

64MB

64

TE0808


TE0803-

04

01-

09EG

03CG-

1EB

1E

9eg

3cg_

1eb_

sk

REV04

REV01

4GB

2GB

64MB

64

TE0808


TE0803-

04

01-

09EG

02EG-

1ED

1EA

9eg_1eb

2eg_sk

REV04

REV01

4GB

2GB

64MB2,5 mm connector

128
TE0803-01-02CG-1EA	2cg

TE0808-04-09EG-1EE9eg_1eb

_sk

REV04

REV01

4GB

2GB

128MB

128

TE0808


TE0803-

04

01-

09EG

03EG-

1EL

1EA

9eg

3eg_

1eb_

sk

REV04

REV01

4GB

2GB

128MB2,5 mm connectorTE0808-04-09EG-2IB9eg_2ib

128
TE0803-01-03CG-1EA	3cg_sk

REV04

REV01

4GB

2GB

64MBTE0808-04-09EG-2IE9eg_2ib_skREV044GB128MBTE0808-04-15EG-1EB15eg_1eb_skREV044GB64MBTE0808-04-15EG-1EE15eg_1eb_skREV044GB128MB

Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.

128

Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.

Design supports following carriersDesign supports following carriers:

Carrier Model	Notes
TEBF0808	Used as reference carrier.

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Additional Sources

Type	Location	Notes
SI5345SI5338	<design name>/misc/Si5345Si5338	SI5345 SI5338 Project with current PLL Configuration

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Reference Design is available on:

TE0808 TE0803 "StarterKit" Reference Design

Design Flow

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Prepare HW like described on section 46042664 Programming
Connect UART USB (JTAG XMOD)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used.
(Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
(Optional) Connect Sata Disc
(Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
(Optional) Connect Network Cable
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.

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Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block

language	ruby
title	_i_io.xdc


# system controller ip
set_property PACKAGE_PIN A13

Code Block

language	ruby
title	_i_io.xdc


#LED_HD SC0 J3:31
set_property PACKAGE_PIN J14 [get_ports {LED_HD[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_HD[0]}]
#LED_XMOD SC17 J3:48 
set_property PACKAGE_PIN B13 [get_ports {LED_XMOD2[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_XMOD2[0]}]

#System Controller IP
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_sc7io]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B13 [get_ports BASE_sc10_iosc11]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18A14 [get_ports BASE_sc11sc12]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B14 [get_ports BASE_sc12sc13]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18F13 [get_ports BASE_sc13sc14]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18G13 [get_ports BASE_sc14sc15]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18D15 [get_ports BASE_sc15sc5]

# PLL
#setset_property PACKAGE_PIN AH6H13 [get_ports {si570_clk_p[0]}BASE_sc6]
#setset_property IOSTANDARDPACKAGE_PIN LVDSH14 [get_ports {si570_clk_p[0]}BASE_sc7]
#setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_n[0]}]
# Clocks
#setBASE_sc5]
set_property PACKAGE_PINIOSTANDARD J8LVCMOS18 [get_ports {B229_CLK1_clk_p[0]}]
#setBASE_sc6]
set_property PACKAGE_PINIOSTANDARD F25LVCMOS18 [get_ports {B128_CLK0_clk_p[0]}]
# SFP 
#setBASE_sc7]
set_property PACKAGE_PINIOSTANDARD G8LVCMOS18 [get_ports {B230BASE_CLK0_clk_p}]
# B230_RX3_P
#setsc10_io]
set_property PACKAGE_PINIOSTANDARD A4LVCMOS18 [get_ports {SFP1BASE_rxp}sc11]
# B230_TX3_P
#set_property PACKAGE_PIN A8set_property IOSTANDARD LVCMOS18 [get_ports {SFP1BASE_txp}sc12]
# B230_RX2_P
#set_property PACKAGE_PIN B2set_property IOSTANDARD LVCMOS18 [get_ports {SFP2BASE_rxp}sc13]
# B230_TX2_P
#set_property PACKAGE_PIN B6set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports {SFP2BASE_txp}sc15]

# Audio Codec
#LRCLK          J3:49 B47_L9_N
#BCLK            J3:51 B47_L9_P
#DAC_SDATA    J3:53 B47_L7_N
#ADC_SDATA    J3:55 B47_L7_P 
#ADC_SDATA    J3:55 
set_property PACKAGE_PIN L13 [get_ports LRCLK ]
set_property PACKAGE_PIN L14 [get_ports BCLK ]
set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ]
set_property PACKAGE_PINIOSTANDARD G14LVCMOS18 [get_ports LRCLK ]
set_property PACKAGE_PINIOSTANDARD G15LVCMOS18 [get_ports BCLK ]
set_property PACKAGE_PINIOSTANDARD E15LVCMOS18 [get_ports DAC_SDATA ]
set_property PACKAGE_PINIOSTANDARD F15LVCMOS18 [get_ports ADC_SDATA ]
#LED
#LED_HD SC0 J3:31
set_property IOSTANDARDPACKAGE_PIN LVCMOS18G14 [get_ports LRCLK {LED_HD[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ] [get_ports {LED_HD[0]}]
#LED_XMOD SC17 J3:48 
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B15 [get_ports DAC_SDATA {LED_XMOD2[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA {LED_XMOD2[0]}]

# CAN
#CAN RX SC19 J3:52 B47B26_L2L11_P
#CAN TX SC18 J3:50 B47B26_L2L11_N
#CAN S  SC16 J3:46 B47B26_L3L1_N

set_property PACKAGE_PIN A13A15 [get_ports CAN_0_S ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_S ]
set_property PACKAGE_PIN B14K14 [get_ports CAN_0_rx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_rx ]
set_property PACKAGE_PIN A14J14 [get_ports CAN_0_tx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

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zynqmp_fsbl

TE modified 2017.4 FSBL

Changes:

Si5345ConfigurationSi5338Configuration, PCIe Reset over GPIO see xfsbl_board.c and xfsbl_board.h
Add Si5345-Registersregister_map.h, si5345si5338.c, si5345si5338.h

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

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Xilinx default PMU firmware.

Hello

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TE0803

Hello TE0808 TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

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HTML
<!-- Add Description for other Software, for example SI CLK Builder ... -->

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SI5338

Download ClockBuilder Pro Desktop for SI5345SI5338

Install and start ClockBuilderClockBuilder
Select SI5338
Options → Open register map file
Note: File location <design name>Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"Si5338/RegisterMap.txt
Modify settings
Export → Register File → select C code header → save to fileOptions → save C code header files
Replace Header files from FSBL template with generated file

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Release 2017.2

Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

	modified-user
	modified-user

Update Documentation only

2018-01-17

v.7

John Hartfiel

Update Design

2018-01-15

v.4

John Hartfiel

Release 2017.4

2017-12-20

v.2

John Hartfiel

(working in process)

All

Page info

	modified-users
	modified-users

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Trenz Electronic Documentation

Versions Compared

Old Version 1

New Version 2

Key

Release Notes and Know Issues

Requirements

Software

Requirements

Software

Additional Sources

Design Flow

Basic module constrains

Design specific constrain

Design specific constrain

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

Hello

TE0803

SI5338