Page History
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Name / opt. VHD Name | Direction | Pin | Description |
---|---|---|---|
C_TCK | in | 30 | JTAG B2B |
C_TDI | in | 32 | JTAG B2B |
C_TDO | out | 1 | JTAG B2B |
C_TMS | in | 29 | JTAG B2B |
EN1 | in | 27 | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback |
ERR_OUT | in | 4 | PS_ERROR_OUT, see ug1085 |
ERR_STATUS | in | 5 | PS_ERROR_STATUS, see ug1085 / currently_not_used |
JTAGEN | in | 26 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
MODE | in | 25 | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) |
MODE0 | out | 12 | ZynqMP Boot Mode Pin 0 |
MODE1 | out | 13 | ZynqMP Boot Mode Pin 1 |
MODE2 | out | 14 | ZynqMP Boot Mode Pin 2 |
MODE3 | out | 16 | ZynqMP Boot Mode Pin 3 |
NOSEQ | inout | 23/ currently_not_used | usage CPLD Variant depends |
PGOOD | out | 28 | Module Power Good. |
PHY_LED1 | in | 17 | ETH PHY LED1 |
TCK | out | 9 | JTAG ZynqMP |
TDI | out | 8 | JTAG ZynqMP |
TDO | in | 10 | JTAG ZynqMP |
TMS | out | 11 | JTAG ZynqMP |
X0 | out | 20 | FPGA IO / Firmware Variant |
X1 | out | 21 | FPGA IO / PHY_LED1 |
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
Boot Mode
2 Boot Modes can be selected via B2B Pin Mode. For other options Firmware update is necessary. Trenz Electronic provides currently 2 4 Firmware variants, one for SD and /JTAG, one for JTAG/QSPI, one for SD/QSPI and SD/QSPI/JTAG usage.
Mode | JTAG/QSPI-Variant | SD/JTAG-Variant | |||
---|---|---|---|---|---|
Zero | JTAG | Boot from SD | |||
SD/QSPI (default Firmware) | SD/QSPI/JTAG | ||||
low | JTAG | Boot from SD | Boot from SD | JTAG Mode, if NOSEQ* is high otherwise boot from SD | |
high | Boot from Flash | JTAG | OneBoot from Flash | JTAG Mode, if NOSEQ* is high otherwise boot from Flash |
For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.
Note |
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Set Boot Mode to JTAG, A special FSBL is provided on 2017.4 or newer reference designs to write boot image to QSPI with Xilinx tools (Vivado or SDK) on Boot Mode unequal JTAG . |
Note |
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NOSEQ*: Please check the carrierboard documentation, before using the SD/QSPI/JTAG firmware variant on TE0820. In the most cases special carrier CPLD firmware is needed. |
Power
PGOOD is EN1 and not ER_OUT. There is no additional power management controlled by CPLD.
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X0/X1 Pin
Pin | Description | |||
---|---|---|---|---|
X0 | Firmware Variant: 0 SD boot, 1: QSPI | X1 | PHY_LED1* | indicate firmware variant and NOSEQ status |
X1 | PHY_LED1 |
*It's recommended to forward this signal to a carrier LED if status check is needed.
Firmware Variant | Blink sequence | Condition |
---|---|---|
QSPI/JTAG | *ooooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
JTAG/SD | **oooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
QSPI/SD | ****oooo/******** | ****oooo if NOSEQ='1' or ******** if NOSEQ='0' |
SD/QSPI/JTAG | ***ooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
Appx. A: Change History
Revision Changes
- REV02 to REV03
- new Boot Mode variants
- new X0 status blink sequencing
- REV01 to REV02
- Boot Mode variants
- X1
- Remove ERR_STATUS
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV02REV03 | REV02, REV01 |
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2018-01-10 | v.10 | REV02 | REV02, REV01 | John Hartfiel |
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2017-08-21 | v.9 | REV02 | REV02, REV01 | John Hartfiel |
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2017-08-17 | v.8 | REV02 | REV02, REV01 | John Hartfiel |
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2017-06-08 | v.4 | REV01 | REV01 | John Hartfiel |
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2017-03-06 | v.2 | REV01 | REV01 | John Hartfiel |
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2017-03-06 | v.1 | REV01 | REV01 |
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All |
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