Page History
...
| Switch | Position | Description |
|---|---|---|
| S2-1 | ON | Mode control MC1. |
| S2-2 | ON | Mode control MC0.FPGA access on module (need also S2-3 ON) |
S2-3 | ON | JTAG enabled for B2B JB1 connector.FPGA access on module (need also S2-2 ON) |
| S2-4 | OFF | Boot mode set to QSPI. |
...
LEDs D3 and D4 are also connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be controlled by SoM FPGA firmware.
DIP switches
DIP switch settings are CPLD Firmware depends, default firmware:
| Switch | ON | OFF | Notes | ||
|---|---|---|---|---|---|
| S2-1 | User configurable, routed to CPLD | User configurable, routed to CPLD | Force CD Pin to module to GND | set CD Pin to module to SD CD Pin | TE0703 CPLD - CC703S#CC703S-SD |
| S2-2 | User configurable, routed to CPLD | User configurable, routed to CPLD | Module FPGA JTAG access ( if S2-3 ON) | Module CPLD JTAG access ( if S2-3 ON) | TE0703 CPLD - CC703S#CC703S-JTAG |
| S2-3 | JTAG enabled for B2B connector JB2 | JTAG enabled for CPLD | Module FPGA/CPLD JTAG access ( depends on S2-3) | Carrier CPLD JTAG access | TE0703 CPLD - CC703S#CC703S-JTAG |
| S2-4 | Boot from SD Card | Boot from QSPI flash on module | TE0703 CPLD - CC703S#CC703S-BootMode |
Power
Power supply with minimum current capability of 3A for system startup is recommended.
...
Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| John Hartfiel |
| |||||||||
| 2017-11-09 | v.26 | John Hartfiel |
| ||||||||
| 2017-02-21 | v.19 | Jan Kumann |
| ||||||||
| 2017-02-02 | v.16 | Jan Kumann |
| ||||||||
| 2016-12-22 | v.14 | Jan Kumann |
| ||||||||
| 2016-12-08 | v.10 | Jan Kumann |
| ||||||||
| 2016-12-05 | v.5 | John Hartfiel |
| ||||||||
| 2016-09-06 | v.1 | Jan Kumann, John Hartfiel |
|
...
Overview
Content Tools